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參數(shù)資料
| 型號： | LT1218LCS8#TR |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 5/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC OPAMP PREC R-R I/O 5V 8SOIC |
| 標準包裝： | 2,500 |
| 放大器類型： | 通用 |
| 電路數(shù)： | 1 |
| 輸出類型： | 滿擺幅 |
| 轉(zhuǎn)換速率： | 0.1 V/µs |
| 增益帶寬積： | 300kHz |
| 電流 - 輸入偏壓： | 30nA |
| 電壓 - 輸入偏移： | 35µV |
| 電流 - 電源： | 400µA |
| 電流 - 輸出 / 通道： | 12mA |
| 電壓 - 電源，單路/雙路(±)： | 2 V ~ 10 V，±1 V ~ 5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SO |
| 包裝： | 帶卷 (TR) |
13
LT1218/LT1219
Shutdown
The biasing of the LT1218/LT1219 is controlled by the
SHDN pin. When the SHDN pin is low, the part is shut
down. In the shutdown mode, the output looks like a 40pF
capacitor and the supply current is less than 30
A. The
SHDN pin is referenced to the positive supply through an
internal bias circuit (see Figure 1). The SHDN pin current
with the pin low is typically 3
A.
The switching time between the shutdown and active
states is about 20
s, however, the total time to settle will
be greater by the slew time of the amplifier. For example,
if the DC voltage at the amplifier output is 0V in shutdown
and –2V in the active mode, an additional 20
s is required.
Figures 4a and 4b show the switching waveforms for a
sinusoidal and a –2V DC input to the LT1218.
The SHDN pin can be driven directly from CMOS logic if the
logic and the LT1218/LT1219 are operated from the same
supplies. For higher supply operation, an interface is
required. An easy way to interface between supplies is to
use open-drain logic, an example is shown in Figure 5.
Because the SHDN pin is referenced to the positive supply,
the logic used should have a breakdown voltage greater
than the positive supply.
APPLICATIONS INFORMATION
WU
U
VOUT
SHDN
RL = 10V
VS = ±2.5V
LT1218/19 F04a
Figure 4a
VOUT
SHDN
RL = 10V
VS = ±2.5V
LT1218/19 F04a
Figure 4b
0V
+
–
–15V
15V
LT1218/
LT1219
LT1218/19 F05
SHDN
5V
SHDN
74C906
Figure 5. Shutdown Interface
Trim Pins
Trim pins are provided for compatibility with other single
op amps. Input offset voltage can be adjusted over a
±2.3mV range with a 10k potentiometer.
–
+
2
3
4
1
8
7
10k
V–
OUT
V+
LT1218/
LT1219
LT1218/19 F06
Figure 6. Optional Offset Nulling
Improved Supply Rejection in the LT1219
The LT1219 is a variation of the LT1218 offering greater
supply rejection and lower high frequency output imped-
ance. The LT1219 requires a 0.1
F load capacitance for
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