V + 7 6 LT1193 V 鈥� 4 1 8 OUT V + 3 鈥� 2 <" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� LT1193CS8
寤犲晢锛� Linear Technology
鏂囦欢闋佹暩(sh霉)锛� 11/12闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC AMP VIDEO DIF ADJ 8-SOIC
妯欐簴鍖呰锛� 100
鎳夌敤锛� 宸垎
闆昏矾鏁�(sh霉)锛� 1
-3db甯跺锛� 80MHz
杞夋彌閫熺巼锛� 500 V/µs
闆绘祦 - 闆绘簮锛� 35mA
闆绘祦 - 杓稿嚭 / 閫氶亾锛� 50mA
闆诲 - 闆绘簮锛屽柈璺�/闆欒矾(±)锛� 4.75 V ~ 16 V锛�±2.38 V ~ 8 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 8-SOIC锛�0.154"锛�3.90mm 瀵級
渚涙噳鍟嗚ō鍌欏皝瑁濓細 8-SOIC
鍖呰锛� 绠′欢
8
LT1193
1193fb
V +
7
6
LT1193
V 鈥�
4
1
8
OUT
V
+
3
鈥�
2
VIN
SHDN
5
AV = 鈥�
RFB + RG
RG
AV = +
RFB + RG
RG
RFB
7
6
LT1193
4
1
8
VOUT
+
3
鈥�
2
VINDIFF
SHDN
5
VO = (VINDIFF + VIN)
RFB + RG
RG
RFB + RG
RG
RFB
RG
RFB
LT1193 TA03
7
6
LT1193
4
+/REF
1
鈥�/FB
8
VOUT
+
3
鈥�
2
5
VO =
RFB
7
6
LT1193
4
1
8
VOUT
+
3
鈥�
2
VIN
SHDN
5
RFB
VIN
(
( VINDIFF 鈥揤IN
( (
+/REF
鈥�/FB
+/REF
鈥�/FB
+/REF
鈥�/FB
RG
VINDIFF
RG
V +
V 鈥�
V +
V 鈥�
V +
V 鈥�
APPLICATIO S I FOR ATIO
WU
UU
In many applications and those requiring good settling
time it is important to use multiple bypass capacitors. A
0.1
F ceramic disc in parallel with a 4.7F tantalum is
recommended. Two oscilloscope photos with different
bypass conditions are used to illustrate the settling time
characteristics of the amplifier. Note that although the
output waveform looks acceptable at 1V/DIV, when ampli-
fied to 10mV/DIV the settling time to 10mV is 347ns for the
0.1
F bypass; the time drops to 96ns with multiple bypass
capacitors.
Operating With Low Closed-Loop Gains
The LT1193 has been optimized for closed-loop gains of
2 or greater; the frequency response illustrates the ob-
tainable closed-loop bandwidths. For a closed-loop gain
of 2 the response peaks about 2dB. Peaking can be
minimized by keeping the feedback elements below 1k
,
and can be eliminated by placing a capacitor across the
feedback resistor, (feedback zero). This peaking shows
up as time domain overshoot of about 40%. With the
feedback capacitor it is eliminated.
Cable Terminations
The LT1193 video difference amplifier has been optimized
as a low cost cable driver. The
卤50mA guaranteed output
current enables the LT1193 to easily deliver 7.5VP-P into
No Supply Bypass Capacitors
LT1192 TA04
AV = 10, IN DEMO BOARD, RL = 1k
LT1192 TA05
SETTLING TIME TO 10mV, AV = 2
SUPPLY BYPASS CAPACITORS = 0.1
F
VOUT
1V/DIV
0V
LT1192 TA06
SETTLING TIME TO 10mV, AV = 2
SUPPLY BYPASS CAPACITORS = 0.1
F + 4.7F TANTALUM
VOUT
1V/DIV
0V
Settling Time Poor Bypass
Settling Time Good Bypass
0V
VOUT
10mV/DIV
VOUT
10mV/DIV
鐩搁棞PDF璩囨枡
PDF鎻忚堪
MAX5811NEUT+T IC DAC SERIAL 10BIT 1CH SOT23-6
VI-B31-MU-F3 CONVERTER MOD DC/DC 12V 200W
VI-B10-MX-S CONVERTER MOD DC/DC 5V 75W
MAX5811MEUT+T IC DAC SERIAL 10BIT 1CH SOT23-6
VI-B31-MU-F1 CONVERTER MOD DC/DC 12V 200W
鐩搁棞浠ｇ悊鍟�/鎶€琛撳弮鏁�(sh霉)
鍙冩暩(sh霉)鎻忚堪
LT1193CS8#PBF 鍔熻兘鎻忚堪:IC AMP VIDEO DIF ADJ 8-SOIC RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 绶氭€� - 鏀惧ぇ鍣� - 瑕栭牷鏀惧ぇ鍣ㄥ拰闋荤珐娌栧櫒 绯诲垪:- 鐢㈠搧鍩硅〒妯″:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 妯欐簴鍖呰:50 绯诲垪:- 鎳夌敤:TFT-LCD 闈㈡澘锛歏COM 椹呭嫊鍣� 杓稿嚭椤炲瀷:婊挎摵骞� 闆昏矾鏁�(sh霉):1 -3db甯跺:35MHz 杞夋彌閫熺巼:40 V/µs 闆绘祦 - 闆绘簮:3.7mA 闆绘祦 - 杓稿嚭 / 閫氶亾:1.3A 闆诲 - 闆绘簮锛屽柈璺�/闆欒矾(±):9 V ~ 20 V锛�±4.5 V ~ 10 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:8-TSSOP锛�8-MSOP锛�0.118"锛�3.00mm 瀵級瑁搁湶鐒婄洡 渚涙噳鍟嗚ō鍌欏皝瑁�:8-uMax-EP 鍖呰:绠′欢
LT1193CS8#TR 鍔熻兘鎻忚堪:IC AMP VIDEO DIFF ADJUST 8SOIC RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 绶氭€� - 鏀惧ぇ鍣� - 瑕栭牷鏀惧ぇ鍣ㄥ拰闋荤珐娌栧櫒 绯诲垪:- 妯欐簴鍖呰:1,000 绯诲垪:- 鎳夌敤:椹呭嫊鍣� 杓稿嚭椤炲瀷:宸垎 闆昏矾鏁�(sh霉):3 -3db甯跺:350MHz 杞夋彌閫熺巼:1000 V/µs 闆绘祦 - 闆绘簮:14.5mA 闆绘祦 - 杓稿嚭 / 閫氶亾:60mA 闆诲 - 闆绘簮锛屽柈璺�/闆欒矾(±):5 V ~ 12 V锛�±2.5 V ~ 6 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:20-VFQFN 瑁搁湶鐒婄洡 渚涙噳鍟嗚ō鍌欏皝瑁�:20-QFN 瑁搁湶鐒婄洡锛�4x4锛� 鍖呰:甯跺嵎 (TR)
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