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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | LT1122CCN8 |
| 寤犲晢锛� | Linear Technology |
| 鏂囦欢闋佹暩(sh霉)锛� | 13/14闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC OP-AMP JFET FAST-SETTLNG 8DIP |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 50 |
| 鏀惧ぇ鍣ㄩ鍨嬶細 | J-FET |
| 闆昏矾鏁�(sh霉)锛� | 1 |
| 杞�(zhu菐n)鎻涢€熺巼锛� | 75 V/µs |
| 澧炵泭甯跺绌嶏細 | 13MHz |
| 闆绘祦 - 杓稿叆鍋忓锛� | 12pA |
| 闆诲 - 杓稿叆鍋忕Щ锛� | 130µV |
| 闆绘祦 - 闆绘簮锛� | 7.8mA |
| 闆诲 - 闆绘簮锛屽柈璺�/闆欒矾(±)锛� | ±5 V ~ 18 V |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 瀹夎椤炲瀷锛� | 閫氬瓟 |
| 灏佽/澶栨锛� | 8-DIP锛�0.300"锛�7.62mm锛� |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 8-PDIP |
| 鍖呰锛� | 绠′欢 |
LT1122
8
1122fb
For more information www.linear.com/LT1122
APPLICATIONS INFORMATION
Settling Time Measurements
Settling time test circuits shown on some competitive
devices鈥� data sheets require:
1. A鈥渇lattop鈥漰ulsegenerator.Unfortunately,flattoppulse
generators are not commercially available.
2. A variable feedback capacitor around the device under
test. This capacitor varies over a four-to-one range.
Presumably, as each op amp is measured for settling
time, the capacitor is fine tuned to optimize settling
time for that particular device.
3. A small inductor load to optimize settling.
TheLT1122鈥檚settlingtimeis100%testedinthetestcircuit
shown. No 鈥渇lat top鈥� pulse generator is required. The test
circuit can be readily constructed, using commercially
available ICs. Of course, standard high frequency board
construction techniques should be followed. All LT1122s
are measured with a constant feedback capacitor. No fine
tuning is required.
Speed Boost/Overcompensation Terminal
Pin 8 of the LT1122 can be used to change the input stage
operating current of the device. Shorting Pin 8 to the posi-
tive supply (Pin 7) increases slew rate and bandwidth by
about 25%, but at the expense of a reduction in phase
marginbyapproximately18degrees.Unity-gaincapacitive
load handling decreases from typically 500pF to 100pF.
Conversely,connectinga15kresistorfromPin8toground
pulls 1mA out of Pin 8 (with V+ = 15V). This reduces slew
rate and bandwidth by 25%. Phase margin and capacitive
load handling improve; the latter typically increasing to
800pF.
High Speed Operation
As with most high speed amplifiers, care should be
taken with supply decoupling, lead dress and component
placement.
ThepowersupplyconnectionstotheLT1122mustmaintain
a low impedance to ground over a bandwidth of 20MHz.
This is especially important when driving a significant
resistive or capacitive load, since all current delivered to
the load comes from the power supplies. Multiple high
qualitybypasscapacitorsarerecommendedforeachpower
supply line in any critical application. A 0.1F ceramic and
a 1F electrolytic capacitor, as shown, placed as close as
possible to the amplifier (with short lead lengths to power
supply common) will assure adequate high frequency
bypassing, in most applications.
V+
7
2
6
3
4
1F
0.1F
1F
0.1F
V鈥�
LT1122
1122 TA03
+
鈥�
+
When the feedback around the op amp is resistive (RF),
a pole will be created with RF, the source resistance and
capacitance (RS, CS), and the amplifier input capacitance
(CIN 鈮� 4pF). In low closed-loop gain configurations and
with RS and RF in the kilohm range, this pole can create
excess phase shift and even oscillation. A small capaci-
tor (CF) in parallel with RF eliminates this problem. With
RS (CS + CIN) = RFCF, the effect of the feedback pole is
completely removed.
RS
CS
CIN
RF
CF
OUTPUT
+
鈥�
1122 TA04
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| C2Q 1.25 | FUSE 1.25 32V 0603 FAST C2Q |
| LT1057S8#TRPBF | IC PREC OP-AMP JFET DUAL 8SOIC |
| RC0805FR-07324RL | RES 324 OHM 1/8W 1% 0805 SMD |
| P4SMA440AHE3/5A | TVS 300W 440V 5% UNIDIR SMA |
| RC0805FR-073K83L | RES 3.83K OHM 1/8W 1% 0805 SMD |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| LT1122CCN8#PBF | 鍔熻兘鎻忚堪:IC OP-AMP JFET FAST-SETTLNG 8DIP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> Linear - Amplifiers - Instrumentation 绯诲垪:- 妯�(bi膩o)婧�(zh菙n)鍖呰:100 绯诲垪:- 鏀惧ぇ鍣ㄩ鍨�:閫氱敤 闆昏矾鏁�(sh霉):1 杓稿嚭椤炲瀷:- 杞�(zhu菐n)鎻涢€熺巼:0.2 V/µs 澧炵泭甯跺绌�:- -3db甯跺:- 闆绘祦 - 杓稿叆鍋忓:100pA 闆诲 - 杓稿叆鍋忕Щ:30µV 闆绘祦 - 闆绘簮:380µA 闆绘祦 - 杓稿嚭 / 閫氶亾:- 闆诲 - 闆绘簮锛屽柈璺�/闆欒矾(±):±2 V ~ 18 V 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:8-SOIC锛�0.154"锛�3.90mm 瀵級 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:8-SO 鍖呰:绠′欢 |
| LT1122CCN8PBF | 鍒堕€犲晢:Linear Technology 鍔熻兘鎻忚堪:LT1122CCN8PBF |
| LT1122CM | 鍒堕€犲晢:LINER 鍒堕€犲晢鍏ㄧū:Linear Technology 鍔熻兘鎻忚堪:Fast Settling, JFET Input Operational Amplifier |
| LT1122CMJ8 | 鍒堕€犲晢:LINER 鍒堕€犲晢鍏ㄧū:Linear Technology 鍔熻兘鎻忚堪:Fast Settling, JFET Input Operational Amplifier |
| LT1122CS | 鍒堕€犲晢:LINER 鍒堕€犲晢鍏ㄧū:Linear Technology 鍔熻兘鎻忚堪:Fast Settling, JFET Input Operational Amplifier |
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