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參數(shù)資料
| 型號(hào)： | LT1082 |
| 廠商： | Linear Technology Corporation |
| 元件分類(lèi)： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | 1A High Voltage, Efficiency Switching Voltage Regulator(１Ａ，高壓，高效率開(kāi)關(guān)穩(wěn)壓器) |
| 中文描述： | 1A條高電壓，效率開(kāi)關(guān)穩(wěn)壓器（1A中，高壓，高效率開(kāi)關(guān)穩(wěn)壓器） |
| 文件頁(yè)數(shù)： | 9/12頁(yè) |
| 文件大?。?/td> | 212K |
| 代理商： | LT1082 |
9
LT1082
OPERATIOU
Total power dissipation is the sum of supply current times
input voltage plus switch power:
P
TOT
= (I
IN
)(V
IN
) + P
SW
In a typical example, using negative-to-positive converter
to generate 5V at 0.5A from a –45V input, duty cycle is
approximately 12%, and switch current is about 0.5A,
yielding:
I
IN
= 4.5mA + 0.5(0.004 + DC/28) = 8.7mA
P
SW
= (0.5)
2
1.2
(0.12) = 0.036W
P
TOT
= (45V)(8.7mA) + 0.036 = 0.43W
Temperature rise in a plastic miniDIP would be 90
°
C/W
times 0.43W, or approximately 39
°
C. The maximum am-
bient temperature would be limited to 100
°
C (commercial
temperature limit) minus 39
°
C, or 61
°
C.
In most applications, full load current is used to calculate
die temperature. However, if overload conditions must
also be accounted for, four approaches are possible. First,
if loss of regulated output is acceptable under overload
conditions, the internal thermal limitof the LT1082 will
protect the die in most applications by shutting off switch
current. Thermal limitis not a tested parameter, however,
and should be considered only for noncritical applications
with temporary overloads. A second approach is to use the
larger TO-220 (T) package which, even without a heat sink,
may limit die temperatures to safe levels under overload
conditions. In critical situations, heat sinking of these
packages is required; especially if overload conditions
must be tolerated for extended periods of time.
The third approach for lower current applications is to
leave the second switch emitter (miniDIP only) open. This
increases switch “on” resistance by 2:1, but reduces
switch current limit by 2:1 also, resulting in a net 2:1
reduction in I
2
R switch dissipation under current limit
conditions.
The fourth approach is to clamp the V
C
pin to a voltage less
than its internal clamp level of 2V. The LT1082 switch
current limit is zero at approximately 1V on the V
C
pin and
1.6A at 2V on the V
C
pin. Peak switch current can be
externally clamped between these two levels with a diode.
See AN19 for details.
KT/q = 26mV at 25
°
C
t
S
= pulse width
f
S
= pulse frequency
I
C
= LT1082 V
C
source current (
≈
200
μ
A)
V
C
= LT1082 operating V
C
voltage (1V to 2V)
R3 = resistor used to set mid-frequency “zero” in LT1082
frequency compensation network.
With t
S
= 0.6
μ
s, f
S
= 80kHz, V
C
= 1.5V, and R3 = 2k, offset
voltage shift is
≈
5mV. This is not particularly bothersome,
but note that high offset could result if R3 were reduced to
a much lower value. Also, the synchronizing transistor
must sink higher currents with low values of R3, so larger
drives may have to be used. The transistor must be
capable of pulling the V
C
pin to within 100mV of ground to
ensure synchronizing.
LT1082 Synchronizing
The LT1082 can be externally synchronized in the fre-
quency range of 75kHz to 90kHz. This is accomplished as
shown in the accompanying figures. Synchronizing oc-
curs when the V
C
pin is pulled to ground with an external
transistor. To avoid disturbing the DC characteristics of
the internal error amplifier, the width of the synchronizing
pulse should be under 1
μ
s. C2 sets the pulse width at
≈
0.6
μ
s. The effect of a synchronizing pulse on the LT1082
amplifier offset can be calculated from:
V
KT
q
t
f
I
V
R
I
OS
S
S
C
C
3
C
=
( )( )
+
V
IN
GND
V
C
LT1082
VN2222*
C1
R3
C2
350pF
D2
1N4148
R2
2.2k
D1
1N4148
*SILICONIX OR EQUIVALENT
1082 OP01
FROM 5V
LOGIC
Synchronizing the LT1082
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