4-6
Signal Descriptions
PERR/
AC8
S/T/S
16 mA
Parity Error
may be pulsed active by an agent
that detects a parity error. PERR/ can be used by
any agent to signal data corruption. However, on
detection of a PERR/ pulse, the central resource
may generate a nonmaskable interrupt to the
host CPU, which often implies the system will be
unable to continue operation once error
processing is complete.
SERR/
AB8
O
16 mA
System Error
is an open drain output used to
report address parity errors and data parity errors
on the Special Cycle command.
PAR
AA8
T/S
16 mA
Parity
is the even parity bit that protects the
AD[31:0] and C_BE[3:0]/ lines. Parity covers both
the address and command bits during the
address phase, and both data bits and byte
enables during the data phase.
PAR64
AA17
T/S
16 mA
Parity64
is the even parity bit that protects the
AD[63:32] and C_BE[7:4]/ lines. Parity covers
both the address and command bits during the
address phase, and both data bits and byte
enables during the data phase. This pad contains
an internal 25
μ
A pull-up.
INTA/
V2
O
16 mA
Interrupt
. This signal, when asserted LOW,
indicates that a device is requesting service from
its host device driver.
M66EN
AB10
I
N/A
Enable 66 MHz
is asserted HIGH from the
system if the board is in a 66 MHz slot. This pad
contains an internal 100
μ
A pull-up.
FSELPCI
B8
I
N/A
PCI FSN Select
, when asserted HIGH, selects
the PCI FSN output as the internal PCI Clock
Tree source. This FSN is intended to phase shift
the input PCICLK signal for clock insertion
controllability. The FSN is bypassed automatically
in 33 MHz systems (M66EN deasserted). When
this pin is LOW, the PCI Clock Tree is sourced
directly by the PCICLK signal. This pad contains
an internal 100
μ
A pull-up.
Table 4.1
PCI Interface (Cont.) Signals
Name
BGA Pos
Type
Strength Description