- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄369830 > LQ80221 LAN Transceiver PDF資料下載
參數(shù)資料
| 型號： | LQ80221 |
| 英文描述： | LAN Transceiver |
| 中文描述： | 網(wǎng)絡(luò)收發(fā)器 |
| 文件頁數(shù)： | 52/91頁 |
| 文件大?。?/td> | 907K |
| 代理商： | LQ80221 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁當(dāng)前第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁
80220/80221
MD400159/E
52
The FBI requires 16 signals between he 80220/80221 and
a repeater core. The FBI signal count to a repeater core
will be 16 multiplied by the number of ports, which can be
quite large. The signal count between the 80220/80221
and repeater core can be reduced by 8 per device by
sharing the receive output pins and using RX_EN to
enable only that port where CRS is asserted. Refer to the
Controller Interface section within the Applications section
for more details on RX_EN.
5.9.3 Clocks
Normally, transmit data over the MII/FBI s clocked nto the
80220/80221 with edges from the output clock TX_CLK. It
may be desireable or necessary n some repeater applica-
tions to clock n the transmit data from a master clock from
the repeater core. This would require that transmit data be
clocked in on edges of an input clock. An input clock is
available for clocking in data on TXD with the OSCIN pin.
Notice from the timing diagrams that OSCIN generates
TX_CLK, and TXD data is clocked in on TX_CLK edges.
This means that TXD data is also clocked in on OSCIN
edges as well. Thus, an external clock driving the OSCIN
input can also be used as the clock for TXD.
5.10 SERIAL PORT
5.10.1 General
The 80220/80221 has a MI serial port to access the
devices's configuration inputs and read out the status
outputs. Any external device that has a IEEE 802.3
compliant MI interface can connect directly to the 80220/
80221 without any glue logic, as shown in Figures 11-13.
As described earlier, the MI serial port consists of 8 lines:
MDC, MDIO, MDINT, and MDA[4:0]. However, only 2
lines, MDC and MDIO, are needed to shift data in and out;
MDINT and MDA[4:0] are not needed but are provided for
convenience only.
Note that the MDA[4:0] addresses are inverted inside the
80220/80221 before going to the MI serial port block. This
means that the MDA[4:0] pins would have to be pin
strapped to 11111 externally in order to successfully
match he MI physical address of 00000 on he PHYAD[4:0]
bits internally.
5.10.2 Polling vs. Interrupt
The status output bits can be monitored by either polling
the serial port or with interrupt.
If polling is used, the registers can be read at regular
intervals and the status bits can be checked against their
previous values to determine any changes. To make
polling simpler, all he registers can be accessed n a single
read or write cycle by setting the register address bits
REGAD[4:0] to 11111 and adding enough clocks to read-
out out all the bits, provided the multiple register access
feature has been enabled.
The interrupt feature offers the ability to detect changes in
the status output bits without register polling. Assertion of
interrupt ndicates hat one or more of he status output bits
has changed since the last read cycle. There are three
interrupt output ndicators on the 80220/80221: (1) MDINT
pin, (2) INT bit in the MI serial port Status Output register,
and (3) interrupt pulse on MDIO. These interrupt signals
can be used by an external device to initiate a read cycle.
Then when an nterrupt s detected, he ndividual registers
(or multiple registers) can be read out and the status bits
compared against their previous values to determine any
changes. After the interrupt its have been read out, the
interrupt signals are automatically deasserted. A mask
register bit exists for every status output bit in the Mask
register so that the interrupt bits can be individually pro-
grammed for each application.
5.10.3 Multiple Register Access
If the MI serial port needs to be constantly polled in order
to monitor changes in status output bits, or if it is desired
that all registers be read or written in a singleserial port
access cycle, multiple register access mode can be used.
Multiple register access allows access to all registers in a
single MI serial port access cycle. When multiple register
access is enabled, then all the registers are read/written
when the register address REGAD[4:0]=11111. This
eliminates the need to read or write registers individually.
Multiple register access mode is normally disabled but it
can be enabled by setting the multiple register access
enable bit in the MI serial port Configuration 2 register.
5.10.4 Serial Port Addressing
The device address for the MI serial port are selected by
tying the MDA[4:0] pins to the desired value. MDA[4:0]
share the same pins as the MDINT and PLED[3:0] out-
puts, respectively, as shown Figure 15a. At powerup or
reset, the output drivers are tristated for an interval called
the power-on reset time. During the power-on reset
interval, the value on these pins is latched into the device,
inverted, and used as the MI serial port address. The LED
outputs are open drain with nternal resistor pullup o VCC.
If an LED is desired on the LED outputs, then an LED and
resistor are tied to VCC as shown in Figures 15b. If a high
address is desired, then the LED to VCC automatically
makes the latched address value a high. If a low value for
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LQT100X | Peripheral IC |
| LQT1KX | Peripheral IC |
| LQT50X3 | Peripheral IC |
| LQT60X3 | Peripheral IC |
| LQV3M2768-3CGR | Peripheral IC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LQ821 | 制造商:POLYFET 制造商全稱:Polyfet RF Devices 功能描述:SILICON GATE ENHANCEMENT MODE RF POWER LDMOS TRANSISTOR |
| LQ9D161 | 制造商:SHARP 制造商全稱:Sharp Electrionic Components 功能描述:DEVICE SPECIFICATION FOR TFT-LCD module |
| LQ9D340 | 制造商:SHARP 制造商全稱:Sharp Electrionic Components 功能描述:Color TFT-LCD Module for Measuring instruments/Banking terminals |
| LQA03TC600 | 功能描述:整流器 Q-Series 600V 3A Ultra Low Qrr RoHS:否 制造商:Vishay Semiconductors 產(chǎn)品:Standard Recovery Rectifiers 配置: 反向電壓:100 V 正向電壓下降: 恢復(fù)時間:1.2 us 正向連續(xù)電流:2 A 最大浪涌電流:35 A 反向電流 IR:5 uA 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DO-221AC 封裝:Reel |
| LQA05TC600 | 功能描述:整流器 Q-Series 600V 5A Ultra Low Qrr RoHS:否 制造商:Vishay Semiconductors 產(chǎn)品:Standard Recovery Rectifiers 配置: 反向電壓:100 V 正向電壓下降: 恢復(fù)時間:1.2 us 正向連續(xù)電流:2 A 最大浪涌電流:35 A 反向電流 IR:5 uA 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DO-221AC 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。