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參數(shù)資料
| 型號(hào)： | LPC47S422QFP |
| 廠商： | STANDARD MICROSYSTEMS CORP |
| 元件分類(lèi)： | 外設(shè)及接口 |
| 英文描述： | ENHANCED SUPER I/O WITH LPC INTERFACE FOR SERVER APPLICATIONS |
| 中文描述： | MULTIFUNCTION PERIPHERAL, PQFP100 |
| 封裝： | QFP-100 |
| 文件頁(yè)數(shù)： | 160/264頁(yè) |
| 文件大?。?/td> | 1342K |
| 代理商： | LPC47S422QFP |
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X-BUS INTERFACE
The X-bus interface allows the LPC47S42x to interface to as many as 4 external components that have
an 8 bit data bus and occupy up to 4 contiguous I/O address ports. Depending on the mode of
operation, it provides either 4 separate active low chip selects (nXCS0 – nXCS3) and 2 address pins
(XA0, XA1) or 2 active low chip selects (nXCS0, nXCS0) and 4 address pins (XA0-XA3). It also
provides a read strobe (nXRD), a write strobe (nXWR) and an 8 bit data bus (XD0 – XD7). External
pullups are required on the nXRD and nXWR pins.
The chip select outputs are generated by circuitry in the LPC47S42x that compares the LPC I/O
address bits with the X-bus base I/O address configuration registers. The mode of operation
determines the number of chip selects and address pins that the X-bus interface provides, as well as
the number of bits in the base I/O addresses. The mode is chosen via bit 0 of the X-Bus Selection
Configuration Register located in Logical Device 8 at 0xF0.
In X-Bus Mode 1, the X-bus base I/O address configuration registers contain address bits A15
through A8 and A7 through A2, respectively. A1 and A0 pass directly through to XA1 and XA0,
respectively. The chip selects only become active (low) for the LPC bus cycle in which the address
match occurs.
In X-Bus Mode 2, the X-bus base I/O address configuration registers contain address bits A15
through A8 and A7 through A4, respectively. A3, A2, A1 and A0 pass directly through to XA3, XA2,
XA1 and XA0, respectively. The chip selects only become active (low) for the LPC bus cycle in
which the address match occurs.
The LPC47S42x performs 16-bit address qualification on the X-Bus base I/O addresses. That is, the
upper 4-bits, bits[15:12], must be ‘0’. Note: Bit 6 of the OSC Global Configuration Register (CR24) must
be set to ‘1’ for 16-bit address qualification.
The read and write strobes have address setup and hold times, and pulse widths, that are compatible
with X-Bus timing of the Intel PIIX4. See the timing diagrams in the “Timing” section. The strobes will
only become active during an LPC cycle in which the LPC address matches the corresponding X-bus
address.
Each X-bus chip select has an associated disable bit. This bit allows each chip select to be individually
enabled or disabled. This bit is part of the X-bus Low Address Byte Configuration register.
Each X-bus chip select base address register has an associated “write protect” bit that can only be set
once, and is reset by VCC POR and hard reset (nPCI_RESET). When this bit is set, it prevents the
base address configuration registers (high byte and low byte) for each chip select from being written.
This security feature ensures that the base address and disable bit for each chip select can only be set
by BIOS and cannot be corrupted by any virus software. This bit is part of the X-bus Low Address Byte
Configuration register.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| LPC47S42X | 制造商:SMSC 制造商全稱(chēng):SMSC 功能描述:ENHANCED SUPER I/O WITH LPC INTERFACE FOR SERVER APPLICATIONS |
| LPC47S457-NC | 功能描述:輸入/輸出控制器接口集成電路 Enhanced Super I/O Controller RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| LPC47S457-NS | 功能描述:接口 - 專(zhuān)用 Enhanced Super I/O Controller RoHS:否 制造商:Texas Instruments 產(chǎn)品類(lèi)型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59 |
| LPC47S45X | 制造商:SMSC 制造商全稱(chēng):SMSC 功能描述:Advanced I/O with X-Bus Interface |
| LPC47S45X_07 | 制造商:SMSC 制造商全稱(chēng):SMSC 功能描述:Advanced I/O with X-Bus Interface |
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