
SMSC DS – LPC47M14X 
Page 106 
Rev. 03/19/2001 
PORT 92 FAST GATEA20 AND KEYBOARD RESET 
Port 92 Register 
This port can only be read or written if Port 92 has been enabled via bit 2 of the KRST_GA20 Register (Logical 
Device 7, 0xF0) set to 1.
This register is used to support the alternate reset (nALT_RST) and alternate A20 (ALT_A20) functions. 
NAME 
LOCATION 
DEFAULT VALUE 
ATTRIBUTE 
SIZE 
Port 92 Register 
Bit 
Function 
7:6 
Reserved.  Returns 00 when read 
5 
Reserved.  Returns a 1 when read 
4 
Reserved.  Returns a 0 when read 
3 
Reserved.  Returns a 0 when read 
2 
Reserved.  Returns a 1 when read 
1 
ALT_A20 Signal control.  Writing a 0 to this bit causes the ALT_A20 signal to be 
driven low.  Writing a 1 to this bit causes the ALT_A20 signal to be driven high. 
0 
Alternate System Reset.  This read/write bit provides an alternate system reset 
function.  This function provides an alternate means to reset the system CPU to 
effect a mode switch from Protected Virtual Address Mode to the Real Address 
Mode.  This provides a faster means of reset than is provided by the Keyboard 
controller.  This bit is set to a 0 by a system reset.  Writing a 1 to this bit will cause 
the nALT_RST signal to pulse active (low) for a minimum of 1 μs after a delay of 
500 ns.  Before another nALT_RST pulse can be generated, this bit must be written 
back to a 0. 
nGATEA20 
8042 
P21 
ALT_A20 
0 
0 
0 
1 
1 
0 
1 
1 
Bit 0 of Port 92, which generates the nALT_RST signal, is used to reset the CPU under program control.  This signal 
is AND’ed together externally with the reset signal (nKBDRST) from the keyboard controller to provide a software 
means of resetting the CPU.  This provides a faster means of reset than is provided by the keyboard controller.  
Writing a 1 to bit 0 in the Port 92 Register causes this signal to pulse low for a minimum of 6μs, after a delay of a 
minimum of 14μs.  Before another nALT_RST pulse can be generated, bit 0 must be set to 0 either by a system reset 
of a write to Port 92. Upon reset, this signal is driven inactive high (bit 0 in the Port 92 Register is set to 0). 
If Port 92 is enabled, i.e., bit 2 of KRST_GA20 is set to 1, then a pulse is generated by writing a 1 to bit 0 of the Port 
92 Register and this pulse is AND’ed with the pulse generated from the 8042. This pulse is output on pin KRESET 
and its polarity is controlled by the GPI/O polarity configuration. 
Port 92 
92h 
24h 
Read/Write 
8 bits 
SYSTEM 
nA20M 
0 
1 
1 
1