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參數(shù)資料
| 型號(hào)： | LPC47M14A-NC |
| 廠商： | SMSC Corporation |
| 英文描述： | 128 PIN ENGANCED SUPER I/O CONTROLLER WITH AN LPC INTERFACE AND USB HUB |
| 中文描述： | 128引腳ENGANCED超級(jí)I / O與LPC接口和USB集線器控制器 |
| 文件頁數(shù)： | 5/205頁 |
| 文件大?。?/td> | 1219K |
| 代理商： | LPC47M14A-NC |
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SMSC DS – LPC47M14X
Page 5
Rev. 03/19/2001
6.13.7
6.13.8
6.13.9
6.13.10 Keyboard and Mouse PME Generation................................................................................................109
6.14
GENERAL PURPOSE I/O..........................................................................................................................110
6.14.1
GPIO Pins.............................................................................................................................................110
6.14.2
Description............................................................................................................................................111
6.14.3
GPIO Control........................................................................................................................................112
6.14.4
GPIO Operation....................................................................................................................................112
6.14.5
GPIO PME and SMI Functionality.........................................................................................................113
6.14.6
Either Edge Triggered Interrupts...........................................................................................................114
6.14.7
LED Functionality..................................................................................................................................115
6.15
SYSTEM MANAGEMENT INTERRUPT (SMI)...........................................................................................115
6.15.1
SMI Registers.......................................................................................................................................115
6.16
PME SUPPORT.........................................................................................................................................116
6.16.1
‘Wake on Specific Key’ Option..............................................................................................................117
6.17
FAN SPEED CONTROL AND MONITORING............................................................................................118
6.17.1
Fan Speed Control................................................................................................................................118
6.17.2
Fan Tachometer Inputs.........................................................................................................................119
6.18
SECURITY FEATURE ...............................................................................................................................122
6.18.1
GPIO Device Disable Register Control.................................................................................................122
6.18.2
Device Disable Register .......................................................................................................................122
6.19
GAME PORT LOGIC..................................................................................................................................122
6.19.1
Power Control Register.........................................................................................................................124
6.19.2
VREF Pin..............................................................................................................................................124
RUNTIME REGISTERS......................................................................................................................................125
CONFIGURATION..............................................................................................................................................152
OPERATIONAL DESCRIPTION ........................................................................................................................172
9.1
M
AXIMUM
G
UARANTEED
R
ATINGS
...................................................................................................................172
9.2
DC E
LECTRICAL
C
HARACTERISTICS
................................................................................................................172
10 TIMING DIAGRAMS...........................................................................................................................................177
11 PACKAGE OUTLINE .........................................................................................................................................200
12 APPENDIX - TEST MODE..................................................................................................................................201
12.1
B
OARD
T
EST
M
ODE
.......................................................................................................................................201
12.1.1
XNOR-Chain Test Mode.......................................................................................................................201
13 REFERENCE DOCUMENTS..............................................................................................................................204
14 LPC47M14X REVISIONS...................................................................................................................................205
TABLES
Table 1 – Super I/O Block Addresses........................................................................................................................20
Table 2 – Hub Descriptor to be Modified....................................................................................................................25
Table 3 – Status, Data and Control Registers............................................................................................................27
Table 4 – Tape Select Bits.........................................................................................................................................30
Table 5 – Internal 2 Drive Decode - Normal...............................................................................................................30
Table 6 – Internal 2 Drive Decode - Drives 0 and 1 Swapped ...................................................................................31
Table 7 – Drive Type ID .............................................................................................................................................31
Table 8 – Precompensation Delays ...........................................................................................................................32
Table 9 – Data Rates.................................................................................................................................................33
Table 10 – DRVDEN Mapping ...................................................................................................................................33
Table 11 – Default Precompensation Delays.............................................................................................................33
Table 12 – FIFO Service Delay..................................................................................................................................35
Table 13 – Status Register 0......................................................................................................................................37
Table 14 – Status Register 1......................................................................................................................................38
Table 15 – Status Register 2......................................................................................................................................38
Table 16 – Status Register 3......................................................................................................................................39
Table 17 – Description of Command Symbols...........................................................................................................41
Table 18 – Instruction Set ..........................................................................................................................................43
Table 19 – Sector Sizes.............................................................................................................................................50
Table 20 – Effects of MT and N Bits...........................................................................................................................51
Table 21 – Skip Bit vs Read Data Command.............................................................................................................51
External Clock Signal............................................................................................................................105
Default Reset Conditions......................................................................................................................105
Latches On Keyboard and Mouse IRQs...............................................................................................108
7
8
9
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