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參數(shù)資料
| 型號(hào)： | LPC3230FET296 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | ARM926EJ-S with 256 kB SRAM, USB High-speed OTG, SD-MMC, NAND flash controller, LCD controller |
| 中文描述： | 32-BIT, FLASH, 266 MHz, RISC MICROCONTROLLER, PBGA296 |
| 封裝： | 15 X 15 MM, 0.70 MM PITCH, PLASTIC, MO-216, SOT1048-1, TFBGA-296 |
| 文件頁(yè)數(shù)： | 5/17頁(yè) |
| 文件大?。?/td> | 120K |
| 代理商： | LPC3230FET296 |
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ES_LPC3230
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Errata sheet
Rev. 9 — 1 June 2011
5 of 17
NXP Semiconductors
ES_LPC3230
Errata sheet LPC3230
3. Functional problems detail
3.1 DMA.1: Single burst DMA memory-to-memory transfers have
additional memory cycles when the DMA source memory is on the
EMC bus
Introduction:
The DMA controller is an AHB master that can transfer blocks of data between
peripheral-to-memory, memory-to-peripheral, peripheral-to-peripheral, and
memory-to-memory. In addition to transferring data between memories, a DMA
memory-to-memory flow can be used to transfer blocks of data to / from an FPGA or
external peripheral chip connected to an EMC static memory chip select. When a memory,
FPGA or external peripheral chip does not support burst transfers (i.e. multiple reads for
each active chip select or read strobe) the burst size for that memory-to-memory flow
must be set for one transfer per burst.
Problem:
When using memory-to-memory DMA with the EMC static chip select (EMC_CS[x]_N) as
the DMA source and the DMA channel source burst size is set for a single transfer
(DMACCxControl:SBSIZE = 0), each DMA source read should be a single bus-wide
access. The access should be similar to reading the EMC_CS[x]_N static memory with an
ARM LDR instruction, as shown in
Figure 1
. Note the EMC signal timing for the read is
controlled by the EMCSTATICx registers. In all example scope shots the
EMCSTATICWAITx registers are set to the maximum value.
However, the actual EMC timing for the source DMA read is a double wide chip select with
a burst of two reads (notice how the address increments near the halfway point of nCS0
active), see
Figure 2
. The second data read during the burst is discarded, as the DMA
destination write (also to nCS0 in
Figure 2
) following each read, always writes the first
value read during the read burst. When the DMA source address is set to auto-increment,
the last DMA read transfer will address the last address of the source buffer and the last
source buffer address +1. This behavior only happens during the read part of the DMA
transfer. Memory-to-memory DMA destination writes to the EMC static chip select work as
expected.
Fig 1.
Scope shot 1 - expected read timing
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LPC3230FET296,551 | 功能描述:ARM微控制器 - MCU ARM9 256KRAM VFP USB OTG LCD RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:72 MHz 程序存儲(chǔ)器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風(fēng)格:SMD/SMT |
| LPC3230FET296/01,5 | 功能描述:ARM微控制器 - MCU ARM9 VFP USB OTG Improved LCD RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:72 MHz 程序存儲(chǔ)器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風(fēng)格:SMD/SMT |
| LPC3230FET296/01,551 | 制造商:NXP Semiconductors 功能描述:0 |
| LPC3240 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:16/32-bit ARM microcontrollers; hardware floating-point coprocessor, USB On-The-Go, and EMC memory interface |
| LPC3240FET296 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:16/32-bit ARM microcontrollers; hardware floating-point coprocessor, USB On-The-Go, and EMC memory interface |
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