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| 型號： | LPC2925FBD100 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | ARM9 microcontroller with CAN, LIN, and USB |
| 中文描述： | 32-BIT, FLASH, 125 MHz, RISC MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT407-1, LQFP-100 |
| 文件頁數(shù)： | 28/84頁 |
| 文件大?。?/td> | 551K |
| 代理商： | LPC2925FBD100 |
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LPC2921_23_25_3
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 14 April 2010
28 of 84
NXP Semiconductors
LPC2921/2923/2925
ARM9 microcontroller with CAN, LIN, and USB
6.12.5.3
Clock description
The SPI modules are clocked by two different clocks; CLK_SYS_PESS and CLK_SPIx
(x = 0, 1, 2), see
Section 6.7.2
. Note that each SPI has its own CLK_SPIx branch clock for
power management. The frequency of all clocks CLK_SPIx is identical as they are derived
from the same base clock BASE_CLK_SPI. The register interface towards the system bus
is clocked by CLK_SYS_PESS. The serial-clock rate divisor is clocked by CLK_SPIx.
The SPI clock frequency can be controlled by the CGU. In master mode the SPI clock
frequency (CLK_SPIx) must be set to at least twice the SPI serial clock rate on the
interface. In slave mode CLK_SPIx must be set to four times the SPI serial clock rate on
the interface.
6.12.6
General-purpose I/O
The LPC2921/2923/2925 contains two general-purpose I/O ports located at different
peripheral base addresses. All I/O pins are bidirectional, and the direction can be
programmed individually. The I/O pad behavior depends on the configuration
programmed in the port function-select registers.
The key features are:
General-purpose parallel inputs and outputs.
Direction control of individual bits.
Synchronized input sampling for stable input-data values.
All I/O pins default to input at reset to avoid any possible bus conflicts.
6.12.6.1
Functional description
The general-purpose I/O provides individual control over each bidirectional port pin. There
are two registers to control I/O direction and output level. The inputs are synchronized to
achieve stable read-levels.
To generate an open-drain output, set the bit in the output register to the desired value.
Use the direction register to control the signal. When set to output, the output driver
actively drives the value on the output. When set to input, the signal floats and can be
pulled up internally or externally.
6.12.6.2
Pin description
The five GPIO ports in the LPC2921/2923/2925 have the pins listed below. The GPIO pins
are combined with other functions on the port pins of the LPC2921/2923/2925.
Table 16
shows the GPIO pins.
Table 16.
Symbol
GPIO0 pin[31:0]
GPIO1 pin[27:0]
GPIO5 pin[19:18]
GPIO pins
Pin name
P0[31:0]
P1[27:0]
P5[19:18]
Direction
IN/OUT
IN/OUT
IN/OUT
Description
GPIO port x pins 31 to 0
GPIO port x pins 27 to 0
GPIO port x pins 19 and 18
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