參數(shù)資料
型號: LPC2378
廠商: NXP Semiconductors N.V.
英文描述: Single-chip 16-bit/32-bit microcontrollers; 512 kB flash with ISP/IAP, Ethernet, USB 2.0, CAN, and 10-bit ADC/DAC
中文描述: 單芯片16-bit/32-bit微控制器,512的ISP /國際檢察官聯(lián)合會,以太網(wǎng),USB 2.0,CAN和10 kB閃存位的ADC / DAC
文件頁數(shù): 22/54頁
文件大?。?/td> 203K
代理商: LPC2378
LPC2378_1
NXP B.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01 — 6 December 2006
22 of 54
NXP Semiconductors
LPC2378
Fast communication chip
7.11 USB interface
The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a
host and a number (127 maximum) of peripherals. The host controller allocates the USB
bandwidth to attached devices through a token based protocol. The bus supports hot
plugging, unplugging and dynamic configuration of the devices. All transactions are
initiated by the host controller.
The two sets of pins needed by a USB device are named V
BUS
, USB_D+1, USB_D
1,
USB_UP_LED1, USB_CONNECT1, and USB_D+2, USB_D
2, USB_UP_LED2, and
USB_CONNECT2 respectively. At any given time only one of these two sets can be active
and used by the application.
7.11.1
USB device controller
The device controller enables 12 Mbit/s data exchange with a USB host controller. It
consists of register interface, serial interface engine, endpoint buffer memory, and the
DMA controller. The serial interface engine decodes the USB data stream and writes data
to the appropriate end point buffer memory. The status of a completed USB transfer or
error condition is indicated via status registers. An interrupt is also generated if enabled.
The DMA controller when enabled transfers data between the endpoint buffer and the
USB RAM.
7.11.1.1
Features
Fully compliant with USB 2.0 specification (full speed).
Supports 32 physical (16 logical) endpoints with a 4 kB USB buffer.
Supports Control, Bulk, Interrupt and Isochronous endpoints.
Scalable realization of endpoints at run time.
Endpoint Maximum packet size selection (up to USB maximum specification) by
software at run time.
Supports SoftConnect and GoodLink features.
While USB is in the Suspend mode, LPC2378 can enter one of the reduced power
down modes and wake up on a USB activity.
Supports DMA transfers with the DMA RAM of 8 kB on all non-control endpoints.
Allows dynamic switching between CPU-controlled and DMA modes.
Double buffer implementation for Bulk and Isochronous endpoints.
7.12 CAN controller and acceptance filters
The Controller Area Network (CAN) is a serial communications protocol which efficiently
supports distributed real-time control with a very high level of security. Its domain of
application ranges from high speed networks to low cost multiplex wiring.
The CAN block is intended to support multiple CAN buses simultaneously, allowing the
device to be used as a gateway, switch, or router among a number of CAN buses in
industrial or automotive applications.
Each CAN controller has a register structure similar to the NXP SJA1000 and the PeliCAN
Library block, but the 8-bit registers of those devices have been combined in 32-bit words
to allow simultaneous access in the ARM environment. The main operational difference is
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