參數(shù)資料
型號(hào): LPC2365FBD100
廠商: NXP Semiconductors N.V.
元件分類(lèi): 數(shù)學(xué)處理器
英文描述: ARM7 with 256 kB flash, 58 kB SRAM, Ethernet and 10-bit ADC
封裝: LPC2365FBD100<SOT407-1 (LQFP100)|<<http://www.nxp.com/packages/SOT407-1.html<1<Always Pb-free,;
文件頁(yè)數(shù): 9/12頁(yè)
文件大?。?/td> 170K
代理商: LPC2365FBD100
ES_LPC2365
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Errata sheet
Rev. 6 — 20 April 2011
9 of 12
NXP Semiconductors
ES_LPC2365
Errata sheet LPC2365
3.8 ADC.1: External sync inputs not operational
Introduction:
In software-controlled mode (BURST bit is 0), the 10-bit ADC can start conversion by
using the following options in the A/D Control Register:
Problem:
The external start conversion feature, AD0CR:START = 0x2 or 0x3, may not work reliably
and ADC external trigger edges on P2.10 or P1.27 may be missed. The occurrence of this
problem is peripheral clock (pclk) dependent. The probability of error (missing a ADC
trigger from GPIO) is estimated as follows:
For PCLK_ADC = 72 MHz, probability error = 12 %
For PCLK_ADC = 50 MHz, probability error = 6 %
For PCLK_ADC = 12 MHz, probability error = 1.5 %
The probability of error is not affected by the frequency of ADC start conversion edges.
Work-around:
In software-controlled mode (BURST bit is 0), the START conversion options (bits 26:24
set to 0x1 or 0x4 or 0x5 or 0x6 or 0x7) can be used. The user can also start a conversion
by connecting an external trigger signal to a capture input pin (CAPx) from a Timer
peripheral to generate an interrupt. The timer interrupt routine can then start the ADC
conversion by setting the START bits (26:24) to 0x1. The trigger can also be generated
from a timer match register.
Fig 1.
A/D control register options
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