參數(shù)資料
型號(hào): LPC2365FBD100
廠商: NXP Semiconductors N.V.
元件分類(lèi): 數(shù)學(xué)處理器
英文描述: ARM7 with 256 kB flash, 58 kB SRAM, Ethernet and 10-bit ADC
封裝: LPC2365FBD100<SOT407-1 (LQFP100)|<<http://www.nxp.com/packages/SOT407-1.html<1<Always Pb-free,;
文件頁(yè)數(shù): 10/12頁(yè)
文件大?。?/td> 170K
代理商: LPC2365FBD100
ES_LPC2365
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Errata sheet
Rev. 6 — 20 April 2011
10 of 12
NXP Semiconductors
ES_LPC2365
Errata sheet LPC2365
4. AC/DC deviations detail
4.1 n/a
5. Errata notes detail
5.1 Note.1
On each of the following port pins P0.23, P0.24, P0.25, P0.26, P1.30, and P1.31 (when
configured as general purpose input pin (s)), leakage current increases when the input
voltage is Vi
V
DD
I/O + 0.5 V. Care must be taken to limit the current to less than 4 mA by
using a series limiting resistor.
5.2 Note.2
On the LPC2365 Rev D, design changes to the Memory Accelerator Module were made
to enhance timing and general performance. Design changes are intended to enhance
performance in general and will result in minor differences in the code execution timing
between the previous device revisions and rev D. Actual performance impact is code
dependent, some code sequences may speed up while other code sequences may slow
down between the previous device revisions and rev D. This might be observed when
using software delays and in such cases, a hardware timer should be used to generate a
delay instead of a software delay.
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