參數(shù)資料
型號: LPC2294
廠商: NXP Semiconductors N.V.
英文描述: 16/32-bit ARM microcontrollers 256 kB ISP/IAP Flash with CAN, 10-bit ADC and external memory interface
中文描述: 16/32位ARM微控制器的256 KB的供應商/聯(lián)合會與CAN,10閃光位模數(shù)轉(zhuǎn)換器和外部存儲器接口
文件頁數(shù): 24/40頁
文件大小: 188K
代理商: LPC2294
Philips Semiconductors
LPC2292/LPC2294
16/32-bit ARM microcontrollers with external memory interface
Preliminary data
Rev. 01 — 05 February 2004
24 of 40
9397 750 12748
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Three match registers can be used to provide a PWM output with both edges
controlled. Again, the MR0 match register controls the PWM cycle rate. The other
match registers control the two PWM edge positions. Additional double edge
controlled PWM outputs require only two match registers each, since the repetition
rate is the same for all PWM outputs.
With double edge controlled PWM outputs, specific match registers control the rising
and falling edge of the output. This allows both positive going PWM pulses (when the
rising edge occurs prior to the falling edge), and negative going PWM pulses (when
the falling edge occurs prior to the rising edge).
6.20.1
Features
Seven match registers allow up to six single edge controlled or three double edge
controlled PWM outputs, or a mix of both types.
The match registers also allow:
Continuous operation with optional interrupt generation on match.
Stop timer on match with optional interrupt generation.
Reset timer on match with optional interrupt generation.
Single edge controlled PWM outputs all go HIGH at the beginning of each cycle
unless the output is a constant LOW. Double edge controlled PWM outputs can
have either edge occur at any position within a cycle. This allows for both positive
going and negative going pulses.
Pulse period and width can be any number of timer counts. This allows complete
flexibility in the trade-off between resolution and repetition rate. All PWM outputs
will occur at the same repetition rate.
Double edge controlled PWM outputs can be programmed to be either positive
going or negative going pulses.
Match register updates are synchronized with pulse outputs to prevent generation
of erroneous pulses. Software must ‘release’ new match values before they can
become effective.
May be used as a standard timer if the PWM mode is not enabled.
A 32-bit Timer/Counter with a programmable 32-bit Prescaler.
6.21 System control
6.21.1
Crystal oscillator
The oscillator supports crystals in the range of 1 MHz to 30 MHz. The oscillator
output frequency is called f
osc
and the ARM processor clock frequency is referred to
as cclk for purposes of rate equations, etc. f
osc
and cclk are the same value unless
the PLL is running and connected. Refer to
Section 6.21.2 “PLL”
for additional
information.
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