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| 型號： | LPC2220 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 16/32-bit ARM microcontrollers; flashless with 64 kB, with 10-bit ADC and external memory interface |
| 中文描述： | 16/32位 ARM微控制器；64KB的閃存；10位模數(shù)轉(zhuǎn)換和外部存儲器接口 |
| 文件頁數(shù)： | 24/49頁 |
| 文件大?。?/td> | 255K |
| 代理商： | LPC2220 |
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9397 750 14061
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02— 30 May 2005
24 of 49
Philips Semiconductors
LPC2210/2220
16/32-bit ARM microcontrollers with external memory interface
6.14 SPI serial I/O controller
The LPC2210/2220 contains two SPIs. The SPI is a full duplex serial interface, designed
to be able to handle multiple masters and slaves connected to a given bus. Only a single
master and a single slave can communicate on the interface during a given data transfer.
During a data transfer the master always sends a byte of data to the slave, and the slave
always sends a byte of data to the master.
6.14.1
Features
Compliant with SPI specification.
Synchronous, Serial, Full Duplex, Communication.
Combined SPI master and slave.
Maximum data bit rate of one eighth of the input clock rate.
6.15 SSP controller
This peripheral is available in LPC2220 only.
6.15.1
Features
Compatible with Motorola’s SPI, TI’s 4-wire SSI, and National Semiconductor’s
Microwire buses.
Synchronous Serial Communication.
Master or slave operation.
8-frame FIFOs for both transmit and receive.
Four to 16 bits per frame.
6.15.2
Description
The SSP is a controller capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can
interact with multiple masters and slaves on the bus. Only a single master and a single
slave can communicate on the bus during a given data transfer. Data transfers are in
principle full duplex, with frames of four to 16 bits of data flowing from the master to the
slave and from the slave to the master.
While the SSP and SPI1 peripherals share the same physical pins, it is not possible to
have both of these two peripherals active at the same time. Application can switch on the
fly from SPI1 to SSP and back.
6.16 General purpose timers
The Timer/Counter is designed to count cycles of the peripheral clock (PCLK) or an
externally supplied clock and optionally generate interrupts or perform other actions at
specified timer values, based on four match registers. It also includes four capture inputs
to trap the timer value when an input signal transitions, optionally generating an interrupt.
Multiple pins can be selected to perform a single capture or match function, providing an
application with ‘or’ and ‘a(chǎn)nd’, as well as ‘broadcast’ functions among them.
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