參數(shù)資料
型號: LPC2131
廠商: NXP Semiconductors N.V.
英文描述: Single-chip 16/32-bit microcontrollers; 32/64/512 kB ISP/IAP Flash with 10-bit ADC and DAC
中文描述: 16/32位 單片微控制器;有10位數(shù)模/模數(shù)轉(zhuǎn)換,32/64/512kB的ISP/IAP flash閃存
文件頁數(shù): 21/41頁
文件大?。?/td> 190K
代理商: LPC2131
9397 750 14868
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Preliminary data sheet
Rev. 02 — 15 April 2005
21 of 41
Philips Semiconductors
LPC2131/2132/2134/2136/2138
Single-chip 16/32-bit microcontrollers
6.13 UARTs
The LPC2131/2132/2134/2136/2138 each contain two UARTs. In addition to standard
transmit and receive data lines, the LPC2134/2136/2138 UART1 also provides a full
modem control handshake interface.
6.13.1
Features
16 byte Receive and Transmit FIFOs.
Register locations conform to ‘550 industry standard.
Receiver FIFO trigger points at 1, 4, 8, and 14 bytes
Built-in baud rate generator.
Standard modem interface signals included on UART1. (LPC2134/2136/2138 only)
The LPC2131/2132/2134/2136/2138 transmission FIFO control enables
implementation of software (XON/XOFF) flow control on both UARTs and hardware
(CTS/RTS) flow control on the LPC2134/2136/2138 UART1 only.
6.14 I
2
C-bus serial I/O controller
The LPC2131/2132/2134/2136/2138 each contain two I
2
C-bus controllers.
The I
2
C-bus is bi-directional, for inter-IC control using only two wires: a serial clock line
(SCL), and a serial data line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (e.g., an LCD driver or a transmitter with the
capability to both receive and send information (such as memory)). Transmitters and/or
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. The I
2
C-bus is a multi-master bus, it can be
controlled by more than one bus master connected to it.
The I
2
C-bus implemented in LPC2131/2132/2134/2136/2138 supports bit rates up to
400 kbit/s (Fast I
2
C).
6.14.1
Features
Standard I
2
C compliant bus interface.
Easy to configure as Master, Slave, or Master/Slave.
Programmable clocks allow versatile rate control.
Bidirectional data transfer between masters and slaves.
Multi-master bus (no central master).
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
The I
2
C-bus may be used for test and diagnostic purposes.
相關(guān)PDF資料
PDF描述
LPC2132 Single-chip 16/32-bit microcontrollers; 32/64/512 kB ISP/IAP Flash with 10-bit ADC and DAC
LPC2142 Single-chip 16-bit/32-bit microcontrollers; up to 512 kB flash with ISP/IAP, USB 2.0 full-speed device, 10-bit ADC and DAC
LPC2141 Single-chip 16-bit/32-bit microcontrollers; up to 512 kB flash with ISP/IAP, USB 2.0 full-speed device, 10-bit ADC and DAC
LPC2144 Single-chip 16-bit/32-bit microcontrollers; up to 512 kB flash with ISP/IAP, USB 2.0 full-speed device, 10-bit ADC and DAC
LPC2146 Single-chip 16-bit/32-bit microcontrollers; up to 512 kB flash with ISP/IAP, USB 2.0 full-speed device, 10-bit ADC and DAC
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