參數(shù)資料
型號(hào): LPC2131
廠商: NXP Semiconductors N.V.
英文描述: Single-chip 16/32-bit microcontrollers; 32/64/512 kB ISP/IAP Flash with 10-bit ADC and DAC
中文描述: 16/32位 單片微控制器;有10位數(shù)模/模數(shù)轉(zhuǎn)換,32/64/512kB的ISP/IAP flash閃存
文件頁(yè)數(shù): 14/41頁(yè)
文件大?。?/td> 190K
代理商: LPC2131
9397 750 14868
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Preliminary data sheet
Rev. 02 — 15 April 2005
14 of 41
Philips Semiconductors
LPC2131/2132/2134/2136/2138
Single-chip 16/32-bit microcontrollers
Fast Interrupt reQuest (FIQ) has the highest priority. If more than one request is assigned
to FIQ, the VIC combines the requests to produce the FIQ signal to the ARM processor.
The fastest possible FIQ latency is achieved when only one request is classified as FIQ,
because then the FIQ service routine can simply start dealing with that device. But if more
than one request is assigned to the FIQ class, the FIQ service routine can read a word
from the VIC that identifies which FIQ source(s) is (are) requesting an interrupt.
Vectored IRQs have the middle priority. Sixteen of the interrupt requests can be assigned
to this category. Any of the interrupt requests can be assigned to any of the 16 vectored
IRQ slots, among which slot 0 has the highest priority and slot 15 has the lowest.
Non-vectored IRQs have the lowest priority.
The VIC combines the requests from all the vectored and non-vectored IRQs to produce
the IRQ signal to the ARM processor. The IRQ service routine can start by reading a
register from the VIC and jumping there. If any of the vectored IRQs are requesting, the
VIC provides the address of the highest-priority requesting IRQs service routine,
otherwise it provides the address of a default routine that is shared by all the non-vectored
IRQs. The default routine can read another VIC register to see what IRQs are active.
6.5.1
Interrupt sources
Table 4
lists the interrupt sources for each peripheral function. Each peripheral device has
one interrupt line connected to the Vectored Interrupt Controller, but may have several
internal interrupt flags. Individual interrupt flags may also represent more than one
interrupt source.
Table 4:
Block
WDT
-
ARM Core
ARM Core
TIMER0
Interrupt sources
Flag(s)
Watchdog Interrupt (WDINT)
Reserved for software interrupts only
Embedded ICE, DbgCommRX
Embedded ICE, DbgCommTX
Match 0 to 3 (MR0, MR1, MR2, MR3)
Capture 0 to 3 (CR0, CR1, CR2, CR3)
Match 0 to 3 (MR0, MR1, MR2, MR3)
Capture 0 to 3 (CR0, CR1, CR2, CR3)
RX Line Status (RLS)
Transmit Holding Register empty (THRE)
RX Data Available (RDA)
Character Time-out Indicator (CTI)
RX Line Status (RLS)
Transmit Holding Register empty (THRE)
RX Data Available (RDA)
Character Time-out Indicator (CTI)
Modem Status Interrupt (MSI) (Available in
LPC2134/2136/2138 only)
Match 0 to 6 (MR0, MR1, MR2, MR3, MR4, MR5, MR6)
Capture 0 to 3 (CR0, CR1, CR2, CR3)
SI (state change)
VIC channel #
0
1
2
3
4
TIMER1
5
UART0
6
UART1
7
PWM0
8
I
2
C0
9
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LPC2132 Single-chip 16/32-bit microcontrollers; 32/64/512 kB ISP/IAP Flash with 10-bit ADC and DAC
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