參數(shù)資料
型號(hào): LPC2119FBD64
廠商: NXP Semiconductors N.V.
元件分類: 數(shù)學(xué)處理器
英文描述: Single-chip 16-32-bit microcontrollers; 64-128-256 kB ISP-IAP flash with 10-bit ADC and CAN
封裝: LPC2109FBD64/01<SOT314|<<<1<Always Pb-free,;LPC2119FBD64/01<SOT314-2 (LQFP64)|<<http://www.nxp.com/packages/SOT314-2.html<1<Always Pb-free,;LPC2129FBD64/01<SOT314-2
文件頁數(shù): 17/46頁
文件大小: 291K
代理商: LPC2119FBD64
LPC2109_2119_2129
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 14 June 2011
17 of 46
NXP Semiconductors
LPC2109/2119/2129
Single-chip 16/32-bit microcontrollers
6.12 SPI serial I/O controller
The LPC2109/2119/2129 each contain two SPIs. The SPI is a full duplex serial interface,
designed to be able to handle multiple masters and slaves connected to a given bus. Only
a single master and a single slave can communicate on the interface during a given data
transfer. During a data transfer the master always sends a byte of data to the slave, and
the slave always sends a byte of data to the master.
6.12.1
Features
Compliant with Serial Peripheral Interface (SPI) specification.
Synchronous, Serial, Full Duplex communication.
Combined SPI master and slave.
Maximum data bit rate of
1
8
of the input clock rate.
6.12.2
Features available in LPC2109/2119/2129/01 only
Eight to 16 bits per frame.
When the SPI interface is used in Master mode, the SSELn pin is not needed (can be
used for a different function).
6.13 SSP controller (LPC2109/2119/2129/01 only)
Remark:
This peripheral is available in LPC2109/2119/2129/01 only.
The SSP is a controller capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can
interact with multiple masters and slaves on the bus. Only a single master and a single
slave can communicate on the bus during a given data transfer. Data transfers are in
principle full duplex, with frames of four to 16 bits of data flowing from the master to the
slave and from the slave to the master.
While the SSP and SPI1 peripherals share the same physical pins, it is not possible to
have both of these two peripherals active at the same time. Application can switch on the
fly from SPI1 to SSP and back.
6.13.1
Features
Compatible with Motorola’s SPI, Texas Instrument’s 4-wire SSI, and National
Semiconductor’s Microwire buses.
Synchronous serial communication.
Master or slave operation.
8-frame FIFOs for both transmit and receive.
Four to 16 bits per frame.
6.14 General purpose timers
The Timer/Counter is designed to count cycles of the peripheral clock (PCLK) or an
externally supplied clock and optionally generate interrupts or perform other actions at
specified timer values, based on four match registers. It also includes four capture inputs
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