參數(shù)資料
型號(hào)： LPC2114FBD64
廠商： NXP Semiconductors N.V.
元件分類(lèi)： 數(shù)學(xué)處理器
英文描述： Single-chip 16-32-bit microcontrollers; 128-256 kB ISP-IAP flash with 10-bit ADC
封裝： LPC2114FBD64/01<SOT314-2 (LQFP64)|<<http://www.nxp.com/packages/SOT314-2.html<1<Always Pb-free,;LPC2124FBD64/01<SOT314-2 (LQFP64)|<<http://www.nxp.com/packages/SOT314-2.h
文件頁(yè)數(shù)： 8/42頁(yè)
文件大小： 291K
代理商： LPC2114FBD64
LPC2114_2124
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 10 June 2011
8 of 42
NXP Semiconductors
LPC2114/2124
Single-chip 16/32-bit microcontrollers
P1[16]/
TRACEPKT0
P1[17]/
TRACEPKT1
P1[18]/
TRACEPKT2
P1[19]/
TRACEPKT3
P1[20]/
TRACESYNC
16
O
Trace Packet, bit 0. Standard I/O port with internal pull-up.
12
O
Trace Packet, bit 1. Standard I/O port with internal pull-up.
8
O
Trace Packet, bit 2. Standard I/O port with internal pull-up.
4
O
Trace Packet, bit 3. Standard I/O port with internal pull-up.
48
O
Trace Synchronization. Standard I/O port with internal pull-up.
Note:
LOW on this pin while RESET is LOW, enables pins P1[25:16] to operate as
Trace port after reset.
Pipeline Status, bit 0. Standard I/O port with internal pull-up.
P1[21]/
PIPESTAT0
P1[22]/
PIPESTAT1
P1[23]/
PIPESTAT2
P1[24]/
TRACECLK
P1[25]/EXTIN0
P1[26]/RTCK
44
O
40
O
Pipeline Status, bit 1. Standard I/O port with internal pull-up.
36
O
Pipeline Status, bit 2. Standard I/O port with internal pull-up.
32
O
Trace Clock. Standard I/O port with internal pull-up.
28
24
I
I/O
External Trigger Input. Standard I/O with internal pull-up.
Returned Test Clock output. Extra signal added to the JTAG port. Assists debugger
synchronization when processor frequency varies. Bidirectional pin with internal
pull-up.
Note:
LOW on this pin while RESET is LOW, enables pins P1[31:26] to operate as
Debug port after reset.
Test Data out for JTAG interface.
Test Data in for JTAG interface.
Test Clock for JTAG interface. This clock must be slower than
1
6
of the CPU clock
(CCLK) for the JTAG interface to operate.
Test Mode Select for JTAG interface.
Test Reset for JTAG interface.
pin not connected.
external reset input; a LOW on this pin resets the device, causing I/O ports and
peripherals to take on their default states, and processor execution to begin at
address 0. TTL with hysteresis, 5 V tolerant.
input to the oscillator circuit and internal clock generator circuits.
output from the oscillator amplifier.
ground: 0 V reference.
P1[27]/TDO
P1[28]/TDI
P1[29]/TCK
64
60
56
O
I
I
P1[30]/TMS
P1[31]/TRST
n.c.
RESET
52
20
10
57
I
I
I
XTAL1
XTAL2
V
SS
62
61
6, 18, 25,
42, 50
59
I
O
I
V
SSA
I
analog ground; 0 V reference. This should nominally be the same voltage as V
SS
,
but should be isolated to minimize noise and error.
PLL analog ground; 0 V reference. This should nominally be the same voltage as
V
SS
, but should be isolated to minimize noise and error.
1.8 V core power supply; this is the power supply voltage for internal circuitry.
V
SSA(PLL)
58
I
V
DD(1V8)
17, 49
I
Table 3.
Symbol
Pin description
…continued
Pin
Type Description
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參數(shù)描述
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LPC2114FBD64/01 制造商:NXP Semiconductors 功能描述:MCU 32BIT ARM7TDMI-S 128K 64LQFP 制造商:NXP Semiconductors 功能描述:MCU, 32BIT, ARM7TDMI-S, 128K, 64LQFP 制造商:NXP Semiconductors 功能描述:MCU, 32BIT, ARM7TDMI-S, 128K, 64LQFP, Controller Family/Series:LPC21xx, Core Siz 制造商:NXP Semiconductors 功能描述:MCU, 32BIT, ARM7TDMI-S, 128K, 64LQFP, Controller Family/Series:LPC21xx, Core Size:16bit / 32bit, No. of I/O's:46, Supply Voltage Min:1.65V, Supply Voltage Max:1.95V, Digital IC Case Style:LQFP, No. of Pins:64, Program Memory , RoHS Compliant: Yes
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