參數(shù)資料
型號: LPC2114FBD64
廠商: NXP Semiconductors N.V.
元件分類: 數(shù)學(xué)處理器
英文描述: Single-chip 16-32-bit microcontrollers; 128-256 kB ISP-IAP flash with 10-bit ADC
封裝: LPC2114FBD64/01<SOT314-2 (LQFP64)|<<http://www.nxp.com/packages/SOT314-2.html<1<Always Pb-free,;LPC2124FBD64/01<SOT314-2 (LQFP64)|<<http://www.nxp.com/packages/SOT314-2.h
文件頁數(shù): 17/42頁
文件大?。?/td> 291K
代理商: LPC2114FBD64
LPC2114_2124
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 10 June 2011
17 of 42
NXP Semiconductors
LPC2114/2124
Single-chip 16/32-bit microcontrollers
6.12 SSP controller (LPC2114/2124/01 only)
Remark:
This peripheral is available in LPC2114/2124/01 only.
The SSP is a controller capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can
interact with multiple masters and slaves on the bus. Only a single master and a single
slave can communicate on the bus during a given data transfer. Data transfers are in
principle full duplex, with frames of four to 16 bits of data flowing from the master to the
slave and from the slave to the master.
While the SSP and SPI1 peripherals share the same physical pins, it is not possible to
have both of these two peripherals active at the same time. The application can switch on
the fly from SPI1 to SSP and back.
6.12.1
Features
Compatible with Motorola’s SPI, Texas Instrument’s 4-wire SSI, and National
Semiconductor’s Microwire buses.
Synchronous serial communication.
Master or slave operation.
8-frame FIFOs for both transmit and receive.
Four to 16 bits per frame.
6.13 General purpose timers
The Timer is designed to count cycles of the peripheral clock (PCLK) and optionally
generate interrupts or perform other actions at specified timer values, based on four
match registers. It also includes four capture inputs to trap the timer value when an input
signal transitions, optionally generating an interrupt. Multiple pins can be selected to
perform a single capture or match function, providing an application with ‘or’ and ‘a(chǎn)nd’, as
well as ‘broadcast’ functions among them.
6.13.1
Features
A 32-bit Timer/Counter with a programmable 32-bit Prescaler.
Four 32-bit capture channels per timer that can take a snapshot of the timer value
when an input signal transitions. A capture event may also optionally generate an
interrupt.
Four 32-bit match registers that allow:
Continuous operation with optional interrupt generation on match.
Stop timer on match with optional interrupt generation.
Reset timer on match with optional interrupt generation.
Four external outputs per timer corresponding to match registers, with the following
capabilities:
Set LOW on match.
Set HIGH on match.
Toggle on match.
Do nothing on match.
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