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| 型號(hào)： | LPC2109FBD64 |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 數(shù)學(xué)處理器 |
| 英文描述： | Single-chip 16-32-bit microcontrollers; 64-128-256 kB ISP-IAP flash with 10-bit ADC and CAN |
| 封裝： | LPC2109FBD64/01<SOT314|<<<1<Always Pb-free,;LPC2119FBD64/01<SOT314-2 (LQFP64)|<<http://www.nxp.com/packages/SOT314-2.html<1<Always Pb-free,;LPC2129FBD64/01<SOT314-2 |
| 文件頁數(shù)： | 23/46頁 |
| 文件大?。?/td> | 291K |
| 代理商： | LPC2109FBD64 |
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LPC2109_2119_2129
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 14 June 2011
23 of 46
NXP Semiconductors
LPC2109/2119/2129
Single-chip 16/32-bit microcontrollers
6.18.8
APB
The APB divider determines the relationship between the processor clock (CCLK) and the
clock used by peripheral devices (PCLK). The APB divider serves two purposes. The first
is to provide peripherals with the desired PCLK via APB so that they can operate at the
speed chosen for the ARM processor. In order to achieve this, the APB may be slowed
down to
1
2
to
1
4
of the processor clock rate. Because the APB must work properly at
power-up (and its timing cannot be altered if it does not work since the APB divider control
registers reside on the APB), the default condition at reset is for the APB to run at
1
4
of the
processor clock rate. The second purpose of the APB divider is to allow power savings
when an application does not require any peripherals to run at the full processor rate.
Because the APB divider is connected to the PLL output, the PLL remains active (if it was
running) during Idle mode.
6.19 Emulation and debugging
The LPC2109/2119/2129 support emulation and debugging via a JTAG serial port. A trace
port allows tracing program execution. Debugging and trace functions are multiplexed
only with GPIOs on Port 1. This means that all communication, timer and interface
peripherals residing on Port 0 are available during the development and debugging phase
as they are when the application is run in the embedded system itself.
6.19.1
EmbeddedICE
Standard ARM EmbeddedICE logic provides on-chip debug support. The debugging of
the target system requires a host computer running the debugger software and an
EmbeddedICE protocol convertor. EmbeddedICE protocol convertor converts the Remote
Debug Protocol commands to the JTAG data needed to access the ARM core.
The ARM core has a Debug Communication Channel function built-in. The debug
communication channel allows a program running on the target to communicate with the
host debugger or another separate host without stopping the program flow or even
entering the debug state. The debug communication channel is accessed as a
co-processor 14 by the program running on the ARM7TDMI-S core. The debug
communication channel allows the JTAG port to be used for sending and receiving data
without affecting the normal program flow. The debug communication channel data and
control registers are mapped in to addresses in the EmbeddedICE logic.
The JTAG clock (TCK) must be slower than
1
6
of the CPU clock (CCLK) for the JTAG
interface to operate.
6.19.2
Embedded trace macrocell
Since the LPC2109/2119/2129 have significant amounts of on-chip memory, it is not
possible to determine how the processor core is operating simply by observing the
external pins. The ETM provides real-time trace capability for deeply embedded
processor cores. It outputs information about processor execution to the trace port.
The ETM is connected directly to the ARM core and not to the main AMBA system bus. It
compresses the trace information and exports it through a narrow trace port. An external
trace port analyzer must capture the trace information under software debugger control.
Instruction trace (or PC trace) shows the flow of execution of the processor and provides a
list of all the instructions that were executed. Instruction trace is significantly compressed
by only broadcasting branch addresses as well as a set of status signals that indicate the
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LPC2119FBD64 | Single-chip 16-32-bit microcontrollers; 64-128-256 kB ISP-IAP flash with 10-bit ADC and CAN |
| LPC2129FBD64 | Single-chip 16-32-bit microcontrollers; 64-128-256 kB ISP-IAP flash with 10-bit ADC and CAN |
| LPC2114FBD64 | Single-chip 16-32-bit microcontrollers; 128-256 kB ISP-IAP flash with 10-bit ADC |
| LPC2124FBD64 | Single-chip 16-32-bit microcontrollers; 128-256 kB ISP-IAP flash with 10-bit ADC |
| LPC2131FBD64 | Single-chip 16-32-bit microcontrollers; 32-64-128-256-512 kB ISP-IAP flash with 10-bit ADC and DAC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LPC2109FBD64/00 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Single-chip 16/32-bit microcontrollers; 64/128/256 kB ISP/IAP flash with 10-bit ADC and CAN |
| LPC2109FBD64/00,15 | 制造商:NXP Semiconductors 功能描述: |
| LPC2109FBD64/00,151 | 制造商:NXP Semiconductors 功能描述: |
| LPC2109FBD64/01 | 制造商:NXP Semiconductors 功能描述:MCU, 16BIT/32BIT, 60MHZ, LQFP-64 制造商:NXP Semiconductors 功能描述:MCU, 16BIT/32BIT, 60MHZ, LQFP-64, Controller Family/Series:LPC2100, Core Size:16bit / 32bit, No. of I/O's:46, Supply Voltage Min:1.65V, Supply Voltage Max:1.95V, Digital IC Case Style:LQFP, No. of Pins:64, Program Memory Size:64KB, |
| LPC2109FBD64/01,15 | 功能描述:ARM微控制器 - MCU ARM7 64KF/8KR/CAN RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:72 MHz 程序存儲(chǔ)器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風(fēng)格:SMD/SMT |
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