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| 型號： | LPC2103FHN48 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Single-chip 16-bit-32-bit microcontrollers; 8 kB-16 kB-32 kB flash with ISP-IAP, fast ports and 10-bit ADC |
| 中文描述： | 32-BIT, FLASH, 70 MHz, RISC MICROCONTROLLER, PQCC48 |
| 封裝： | 6 X 6 MM, 0.85 MM HEIGHT, PLASTIC, SOT778-3, HVQFN-48 |
| 文件頁數(shù)： | 19/37頁 |
| 文件大?。?/td> | 192K |
| 代理商： | LPC2103FHN48 |
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LPC2101_02_03_4
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 2 June 2009
19 of 37
NXP Semiconductors
LPC2101/02/03
Single-chip 16-bit/32-bit microcontrollers
6.17.4
Code security (Code Read Protection - CRP)
This feature of the LPC2101/02/03 allows user to enable different levels of security in the
system so that access to the on-chip flash and use of the JTAG and ISP can be restricted.
When needed, CRP is invoked by programming a specific pattern into a dedicated flash
location. IAP commands are not affected by the CRP.
Implemented in bootloader code version 2.21 are three levels of the Code Read
Protection:
1. CRP1 disables access to chip via the JTAG and allows partial flash update (excluding
flash sector 0) using a limited set of the ISP commands. This mode is useful when
CRP is required and flash field updates are needed but all sectors cannot be erased.
2. CRP2 disables access to chip via the JTAG and only allows full flash erase and
update using a reduced set of the ISP commands.
3. Running an application with level CRP3 selected fully disables any access to chip via
the JTAG pins and the ISP. This mode effectively disables ISP override using P0.14
pin, too. It is up to the user’s application to provide (if needed) flash update
mechanism using IAP calls or call reinvoke ISP command to enable flash update via
UART0.
Remark:
Parts LPC2101/02/03 Revision ‘-’ have CRP2 enabled only (bootloader code
version 2.2).
6.17.5
External interrupt inputs
The LPC2101/02/03 include up to three edge or level sensitive external interrupt inputs as
selectable pin functions. When the pins are combined, external events can be processed
as three independent interrupt signals. The external interrupt inputs can optionally be
used to wake-up the processor from Power-down mode and Deep power-down mode.
Additionally all 10 capture input pins can also be used as external interrupts without the
option to wake the device up from Power-down mode.
6.17.6
Memory mapping control
The memory mapping control alters the mapping of the interrupt vectors that appear
beginning at address 0x0000 0000. Vectors may be mapped to the bottom of the on-chip
flash memory, or to the on-chip static RAM. This allows code running in different memory
spaces to have control of the interrupts.
6.17.7
Power control
The LPC2101/02/03 supports three reduced power modes: Idle mode, Power-down
mode, and Deep power-down mode.
CAUTION
If level three Code Read Protection (CRP3) is selected, no future factory testing can be
performed on the device.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LPC2103FHN48,551 | 功能描述:ARM微控制器 - MCU 32K FL/8K RAM 8CH 10-B ADC RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:72 MHz 程序存儲器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風(fēng)格:SMD/SMT |
| LPC2103FHN48H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Single-chip 16-bit/32-bit microcontrollers; 8 kB/16 kB/32 kB flash with ISP/IAP, fast ports and 10-bit ADC |
| LPC2103FHN48H/6 | 制造商:NXP Semiconductors 功能描述:MCU, 16BIT/32BIT, 70MHZ, HVQFN-48 制造商:NXP Semiconductors 功能描述:MCU, 16BIT/32BIT, 70MHZ, HVQFN-48, Controller Family/Series:LPC2100, Core Size:1 |
| LPC2103FHN48H/6,51 | 功能描述:ARM微控制器 - MCU 16bit MCU 8KB FLASH 2KB RAM RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:72 MHz 程序存儲器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風(fēng)格:SMD/SMT |
| LPC2103FHN48H/6,518 | 制造商:NXP Semiconductors 功能描述:0 |
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