參數(shù)資料
型號(hào): LPC2103FHN48
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: Single-chip 16-bit-32-bit microcontrollers; 8 kB-16 kB-32 kB flash with ISP-IAP, fast ports and 10-bit ADC
中文描述: 32-BIT, FLASH, 70 MHz, RISC MICROCONTROLLER, PQCC48
封裝: 6 X 6 MM, 0.85 MM HEIGHT, PLASTIC, SOT778-3, HVQFN-48
文件頁數(shù): 14/37頁
文件大?。?/td> 192K
代理商: LPC2103FHN48
LPC2101_02_03_4
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 2 June 2009
14 of 37
NXP Semiconductors
LPC2101/02/03
Single-chip 16-bit/32-bit microcontrollers
Built-in fractional baud rate generator covering wide range of baud rates without a
need for external crystals of particular values.
Transmission FIFO control enables implementation of software (XON/XOFF) flow
control on both UARTs.
UART1 is equipped with standard modem interface signals. This module also
provides full support for hardware flow control (auto-CTS/RTS).
6.10 I
2
C-bus serial I/O controllers
The LPC2101/02/03 each contain two I
2
C-bus controllers.
The I
2
C-bus is bidirectional, for inter-IC control using only two wires: a Serial Clock Line
(SCL), and a Serial Data Line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (e.g., LCD driver) or a transmitter with the
capability to both receive and send information such as serial memory. Transmitters
and/or receivers can operate in either master or slave mode, depending on whether the
chip has to initiate a data transfer or is only addressed. The I
2
C-bus is a multi-master bus,
it can be controlled by more than one bus master connected to it.
The I
2
C-bus implemented in LPC2101/02/03 supports bit rates up to 400 kbit/s (Fast
I
2
C-bus).
6.10.1
Features
Compliant with standard I
2
C-bus interface.
Easy to configure as Master, Slave, or Master/Slave.
Programmable clocks allow versatile rate control.
Bidirectional data transfer between masters and slaves.
Multi-master bus (no central master).
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
The I
2
C-bus can also be used for test and diagnostic purposes.
6.11 SPI serial I/O controller
The LPC2101/02/03 each contain one SPI controller. The SPI is a full duplex serial
interface, designed to handle multiple masters and slaves connected to a given bus. Only
a single master and a single slave can communicate on the interface during a given data
transfer. During a data transfer the master always sends 8 bits to 16 bits of data to the
slave, and the slave always sends 8 bits to 16 bits of data to the master.
6.11.1
Features
Compliant with SPI specification.
Synchronous, Serial, Full Duplex, Communication.
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