參數(shù)資料
型號(hào)： LPC2103FBD48
廠商： NXP Semiconductors N.V.
元件分類： 數(shù)學(xué)處理器
英文描述： Single-chip 16-bit-32-bit microcontrollers; 8 kB-16 kB-32 kB flash with ISP-IAP, fast ports and 10-bit ADC
封裝： LPC2101FBD48<SOT313-2 (LQFP48)|<<http://www.nxp.com/packages/SOT313-2.html<1<Always Pb-free,;LPC2102FBD48<SOT313-2 (LQFP48)|<<http://www.nxp.com/packages/SOT313-2.html<
文件頁(yè)數(shù)： 9/37頁(yè)
文件大?。?/td> 192K
代理商： LPC2103FBD48
LPC2101_02_03_4
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 2 June 2009
9 of 37
NXP Semiconductors
LPC2101/02/03
Single-chip 16-bit/32-bit microcontrollers
[1]
5 V tolerant (if V
DD(3V3)
and V
DDA
≥
3.0 V) pad providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control.
Open-drain 5 V tolerant (if V
DD(3V3)
and V
DDA
≥
3.0 V) digital I/O I
2
C-bus 400 kHz specification compatible pad. It requires external
pull-up to provide an output functionality. Open-drain configuration applies to ALL functions on that pin.
[2]
[3]
5 V tolerant (if V
DD(3V3)
and V
DDA
≥
3.0 V) pad providing digital I/O (with TTL levels and hysteresis and 10 ns slew rate control) and
analog input function. If configured for an input function, this pad utilizes built-in glitch filter that blocks pulses shorter than 3 ns. When
configured as an ADC input, digital section of the pad is disabled.
[4]
5 V tolerant (if V
DD(3V3)
and V
DDA
≥
3.0 V) pad providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control.
If configured for an input function, this pad utilizes built-in glitch filter that blocks pulses shorter than 3 ns.
[5]
A LOW level during reset on pin P0.14 is considered as an external hardware request to start the ISP command handler.
[6]
Open-drain 5 V tolerant (if V
DD(3V3)
and V
DDA
≥
3.0 V) digital I/O I
2
C-bus 400 kHz specification compatible pad. It requires external
pull-up to provide an output functionality. Open-drain configuration applies only to I
2
C function on that pin.
[7]
Pad provides special analog functionality.
[8]
For lowest power consumption, pin should be left floating when the RTC is not used.
[9]
See LPC2101/02/03 User manual UM10161for details.
V
SS
V
SSA
7, 19, 43
31
I
I
Ground:
0 V reference.
Analog ground:
0 V reference. This should be nominally the same voltage as
V
SS
but should be isolated to minimize noise and error.
Analog 3.3 V power supply:
This should be nominally the same voltage as
V
DD(3V3)
but should be isolated to minimize noise and error. The level on this
pin also provides a voltage reference level for the ADC.
1.8 V core power supply:
This is the power supply voltage for internal
circuitry and the on-chip PLL.
3.3 V pad power supply:
This is the power supply voltage for the I/O ports.
RTC power supply:
3.3 V on this pin supplies the power to the RTC.
V
DDA
42
I
V
DD(1V8)
5
I
V
DD(3V3)
VBAT
17, 40
4
I
I
Table 3.
Symbol
Pin description
…continued
Pin
Type
Description
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