參數(shù)資料
型號(hào): LPC2102FHN48
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: Single-chip 16-bit-32-bit microcontrollers; 8 kB-16 kB-32 kB flash with ISP-IAP, fast ports and 10-bit ADC
中文描述: 32-BIT, FLASH, 70 MHz, RISC MICROCONTROLLER, PQCC48
封裝: 6 X 6 MM, 0.85 MM HEIGHT, PLASTIC, SOT778-3, HVQFN-48
文件頁數(shù): 8/37頁
文件大小: 192K
代理商: LPC2102FHN48
LPC2101_02_03_4
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 2 June 2009
8 of 37
NXP Semiconductors
LPC2101/02/03
Single-chip 16-bit/32-bit microcontrollers
P0.22/AD0.0
32
[3]
I/O
I
I/O
I
I/O
I
I/O
I
I/O
I
I/O
I
P0.22 —
General purpose input/output digital pin.
AD0.0 —
ADC 0, input 0.
P0.23 —
General purpose input/output digital pin.
AD0.1 —
ADC 0, input 1.
P0.24 —
General purpose input/output digital pin.
AD0.2 —
ADC 0, input 2.
P0.25 —
General purpose input/output digital pin.
AD0.6 —
ADC 0, input 6.
P0.26 —
General purpose input/output digital pin.
AD0.7 —
ADC 0, input 7.
P0.27 —
General purpose input/output digital pin.
TRST —
Test Reset for JTAG interface. If DBGSEL is HIGH, this pin is
automatically configured for use with EmbeddedICE (Debug mode).
CAP2.0 —
Capture input for Timer 2, channel 0.
P0.28 —
General purpose input/output digital pin.
TMS —
Test Mode Select for JTAG interface. If DBGSEL is HIGH, this pin is
automatically configured for use with EmbeddedICE (Debug mode).
CAP2.1 —
Capture input for Timer 2, channel 1.
P0.29 —
General purpose input/output digital pin.
TCK —
Test Clock for JTAG interface. This clock must be slower than
1
6
of the
CPU clock (CCLK) for the JTAG interface to operate. If DBGSEL is HIGH, this
pin is automatically configured for use with EmbeddedICE (Debug mode).
CAP2.2 —
Capture input for Timer 2, channel 2.
P0.30 —
General purpose input/output digital pin.
TDI —
Test Data In for JTAG interface. If DBGSEL is HIGH, this pin is
automatically configured for use with EmbeddedICE (Debug mode).
MAT3.3 —
PWM output 3 for Timer 3.
P0.31 —
General purpose output only digital pin.
TDO —
Test Data Out for JTAG interface. If DBGSEL is HIGH, this pin is
automatically configured for use with EmbeddedICE (Debug mode).
Input to the RTC oscillator circuit. Input voltage must not exceed 1.8 V.
Output from the RTC oscillator circuit.
Returned test clock output:
Extra signal added to the JTAG port. Assists
debugger synchronization when processor frequency varies. Bidirectional pin
with internal pull-up.
Input to the oscillator circuit and internal clock generator circuits. Input voltage
must not exceed 1.8 V.
Output from the oscillator amplifier.
Debug select:
When LOW, the part operates normally. When externally
pulled HIGH at reset, P0.27 to P0.31 are configured as JTAG port, and the
part is in Debug mode
[9]
. Input with internal pull-down.
External reset input:
A LOW on this pin resets the device, causing I/O ports
and peripherals to take on their default states and processor execution to
begin at address 0. TTL with hysteresis, 5 V tolerant.
P0.23/AD0.1
33
[3]
P0.24/AD0.2
34
[3]
P0.25/AD0.6
38
[3]
P0.26/AD0.7
39
[3]
P0.27/TRST/
CAP2.0
8
[1]
I
I/O
I
P0.28/TMS/
CAP2.1
9
[1]
I
I/O
I
P0.29/TCK/
CAP2.2
10
[1]
I
I/O
I
P0.30/TDI/
MAT3.3
15
[1]
O
O
O
P0.31/TDO
16
[1]
RTCX1
RTCX2
RTCK
20
[7][8]
25
[7][8]
26
[7]
I
O
I/O
XTAL1
11
I
XTAL2
DBGSEL
12
27
O
I
RST
6
I
Table 3.
Symbol
Pin description
…continued
Pin
Type
Description
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