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參數(shù)資料
| 型號(hào)： | LPC1347FBD48,151 |
| 廠商： | NXP Semiconductors |
| 文件頁(yè)數(shù)： | 28/77頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 32BIT 64KB FLASH 48LQFP |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 系列： | LPC13xx |
| 核心處理器： | ARM? Cortex?-M3 |
| 芯體尺寸： | 32-位 |
| 速度： | 72MHz |
| 連通性： | I²C，Microwire，SPI，SSI，SSP，UART/USART，USB |
| 外圍設(shè)備： | 欠壓檢測(cè)/復(fù)位，POR，WDT |
| 輸入/輸出數(shù)： | 40 |
| 程序存儲(chǔ)器容量： | 64KB（64K x 8） |
| 程序存儲(chǔ)器類型： | 閃存 |
| EEPROM 大?。?/td> | 4K x 8 |
| RAM 容量： | 12K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 48-LQFP |
| 包裝： | 托盤 |
| 其它名稱： | 568-9595 |
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LPC1315_16_17_45_46_47
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 3 — 20 September 2012
34 of 77
NXP Semiconductors
LPC1315/16/17/45/46/47
32-bit ARM Cortex-M3 microcontroller
controlled as needed by changing clock sources, reconfiguring PLL values, and/or altering
the CPU clock divider value. This allows a trade-off of power versus processing speed
based on application requirements. In addition, a register is provided for shutting down the
clocks to individual on-chip peripherals, allowing fine tuning of power consumption by
eliminating all dynamic power use in any peripherals that are not required for the
application. Selected peripherals have their own clock divider which provides even better
power control.
7.18.5.1
Power profiles
The power consumption in Active and Sleep modes can be optimized for the application
through simple calls to the power profile. The power configuration routine configures the
LPC1315/16/17/45/46/47 for one of the following power modes:
Default mode corresponding to power configuration after reset.
CPU performance mode corresponding to optimized processing capability.
Efficiency mode corresponding to optimized balance of current consumption and CPU
performance.
Low-current mode corresponding to lowest power consumption.
In addition, the power profile includes routines to select the optimal PLL settings for a
given system clock and PLL input clock.
Remark: When using the USB, configure the LPC1345/46/47 in Default mode.
7.18.5.2
Sleep mode
When Sleep mode is entered, the clock to the core is stopped. Resumption from the Sleep
mode does not need any special sequence but re-enabling the clock to the ARM core.
In Sleep mode, execution of instructions is suspended until either a reset or interrupt
occurs. Peripheral functions continue operation during Sleep mode and may generate
interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic
power used by the processor itself, memory systems and related controllers, and internal
buses.
7.18.5.3
Deep-sleep mode
In Deep-sleep mode, the LPC1315/16/17/45/46/47 is in Sleep-mode and all peripheral
clocks and all clock sources are off with the exception of the IRC. The IRC output is
disabled unless the IRC is selected as input to the watchdog timer. In addition all analog
blocks are shut down and the flash is in stand-by mode. In Deep-sleep mode, the user has
the option to keep the watchdog oscillator and the BOD circuit running for self-timed
wake-up and BOD protection.
The LPC1315/16/17/45/46/47 can wake up from Deep-sleep mode via reset, selected
GPIO pins, a watchdog timer interrupt, or an interrupt generating USB port activity.
Deep-sleep mode saves power and allows for short wake-up times.
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