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參數(shù)資料
| 型號： | LPC1347FBD48,151 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 22/77頁 |
| 文件大小： | 0K |
| 描述： | IC MCU 32BIT 64KB FLASH 48LQFP |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 系列： | LPC13xx |
| 核心處理器： | ARM? Cortex?-M3 |
| 芯體尺寸： | 32-位 |
| 速度： | 72MHz |
| 連通性： | I²C，Microwire，SPI，SSI，SSP，UART/USART，USB |
| 外圍設(shè)備： | 欠壓檢測/復(fù)位，POR，WDT |
| 輸入/輸出數(shù)： | 40 |
| 程序存儲器容量： | 64KB（64K x 8） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大?。?/td> | 4K x 8 |
| RAM 容量： | 12K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 48-LQFP |
| 包裝： | 托盤 |
| 其它名稱： | 568-9595 |
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LPC1315_16_17_45_46_47
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 3 — 20 September 2012
29 of 77
NXP Semiconductors
LPC1315/16/17/45/46/47
32-bit ARM Cortex-M3 microcontroller
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. The I2C is a multi-master bus and can be
controlled by more than one bus master connected to it.
7.12.1 Features
The I2C-interface is an I2C-bus compliant interface with open-drain pins. The I2C-bus
interface supports Fast-mode Plus with bit rates up to 1 Mbit/s.
Easy to configure as master, slave, or master/slave.
Programmable clocks allow versatile rate control.
Bidirectional data transfer between masters and slaves.
Multi-master bus (no central master).
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
The I2C-bus can be used for test and diagnostic purposes.
The I2C-bus controller supports multiple address recognition and a bus monitor mode.
7.13 12-bit ADC
The LPC1315/16/17/45/46/47 contains one ADC. It is a single 12-bit successive
approximation ADC with eight channels.
7.13.1 Features
12-bit successive approximation ADC.
Input multiplexing among 8 pins and three internal sources.
Low-power mode.
10-bit double-conversion rate mode (conversion rate of up to 1 Msample/s).
Measurement range VREFN to VREFP (typically 3 V; not to exceed VDDA voltage
level).
12-bit conversion rate of up to 500 kHz.
Burst conversion mode for single or multiple inputs.
Optional conversion on transition of input pin or timer match signal.
On the LQFP64 package, power and reference pins (VDDA, VSSA, VREFP, VREFN)
are brought out on separate pins for superior noise immunity.
7.14 General purpose external event counter/timers
The LPC1315/16/17/45/46/47 includes two 32-bit counter/timers and two 16-bit
counter/timers. The counter/timer is designed to count cycles of the system derived clock.
It can optionally generate interrupts or perform other actions at specified timer values,
based on four match registers. Each counter/timer also includes one capture input to trap
the timer value when an input signal transitions, optionally generating an interrupt.
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