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參數(shù)資料
| 型號： | LPC1342FBD48,151 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 15/74頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 32BIT 48LQFP |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 系列： | LPC13xx |
| 核心處理器： | ARM? Cortex?-M3 |
| 芯體尺寸： | 32-位 |
| 速度： | 72MHz |
| 連通性： | I²C，Microwire，SPI，SSI，SSP，UART/USART，USB |
| 外圍設(shè)備： | 欠壓檢測/復(fù)位，POR，WDT |
| 輸入/輸出數(shù)： | 42 |
| 程序存儲器容量： | 16KB（16K x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 4K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 48-LQFP |
| 包裝： | 托盤 |
| 其它名稱： | 568-5214 |
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LPC1311_13_42_43
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 6 June 2012
22 of 74
NXP Semiconductors
LPC1311/13/42/43
32-bit ARM Cortex-M3 microcontroller
The I2C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock Line
(SCL) and a Serial DAta line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the
capability to both receive and send information (such as memory). Transmitters and/or
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. The I2C is a multi-master bus and can be
controlled by more than one bus master connected to it.
7.12.1 Features
The I2C-bus interface is a standard I2C-bus compliant interface with true open-drain
pins. The I2C-bus interface also supports Fast-mode Plus with bit rates up to 1 Mbit/s.
Easy to configure as master, slave, or master/slave.
Programmable clocks allow versatile rate control.
Bidirectional data transfer between masters and slaves.
Multi-master bus (no central master).
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
The I2C-bus can be used for test and diagnostic purposes.
The I2C-bus controller supports multiple address recognition and a bus monitor mode.
7.13 10-bit ADC
The LPC1311/13/42/43 contains one ADC. It is a single 10-bit successive approximation
ADC with eight channels.
7.13.1 Features
10-bit successive approximation ADC.
Input multiplexing among 8 pins.
Power-down mode.
Measurement range 0 V to VDD.
10-bit conversion time
≥ 2.44 μs (up to 400 kSamples/s).
Burst conversion mode for single or multiple inputs.
Optional conversion on transition of input pin or timer match signal.
Individual result registers for each ADC channel to reduce interrupt overhead.
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