參數(shù)資料
型號： LP5551SQX
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 模擬信號調(diào)理
英文描述： PowerWise⑩ Technology Compliant Energy Management Unit
中文描述： SPECIALTY ANALOG CIRCUIT, QCC36
封裝： LLP-36
文件頁數(shù)： 10/32頁
文件大?。?/td> 3081K
代理商： LP5551SQX
Symbol
I
SINK
Parameter
Output Sinking Capability
Conditions
V
DD_A, _D
, P
VDD1,2
= 3.6 V
Bias Current Control bits = 00
V
OUT
> V
OUT(NOM)
- 15 mV(Note 12)
V
DD_A, _D
, P
VDD1,2
= 3.6 V
Bias Current Control bits = 01
V
OUT
> V
OUT(NOM)
- 15 mV(Note 12)
V
DD_A, _D
, P
VDD1,2
= 3.6 V
Bias Current Control bits = 10
V
OUT
> V
OUT(NOM)
- 15 mV(Note 12)
V
DD_A, _D
, P
VDD1,2
= 3.6 V
Bias Current Control bits = 11
V
OUT
> V
OUT(NOM)
- 15 mV(Note 12)
V
DD_A, _D
, P
VDD1,2
= 2.7 V
0μA
≤
I
OUT
≤
3 uA
Min
8
Typ
Max
Units
uA
36
52
80
I
SOURCE
C
LOAD
Output Source Capability
100
uA
Output Capacitance of Load
0.1
1
5
nF
Logic and Control Inputs
and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature
range for operation, -40 to +125°C. (Notes 2, 7, 8, 9)
Unless otherwise noted, V
DD_A, _D
, V
PVDD1,2
, RESETN, ENABLE = 3.6V. Typical values
Symbol
PWI
CLOCK
V
IL
Parameter
Rated frequency
Conditions
2.7 V
≤
V
DD_A, _D
, V
PVDD1,2
≤
5.5 V
ENABLE, RESETN, SPWI, SCLK 2.7
V
≤
V
DD_A, _D
, V
PVDD1,2
≤
5.5 V
ENABLE, RESETN 2.7 V
≤
V
DD_A, _D
,
V
PVDD1,2
≤
5.5 V
SPWI, SCLK, 1.5 V
≤
V
O2
≤
3.3 V
ENABLE, RESETN, 0 V
≤
V
DD_A, _D
,
V
PVDD1,2
≤
5.5 V
SPWI, SCLK, 1.5 V
≤
V
O2
≤
3.3 V
Min
Typ
Max
15
Units
MHz
Input Low Level
0.4
V
V
IH
Input High Level
2
V
V
IH_PWI
I
IL
Input High Level, PWI
V
O2
-0.4V
-5
V
Logic Input Current
5
μA
I
IL_PWI
R
PD_PWI
Logic Input Current, PWI
-5
15
μA
Pull-down resistance for PWI
signals
Minimum low pulse width to
enter STARTUP state
0.5
1
2
M
T
EN_LOW
ENABLE pulsed high - low - high
10
μsec
Logic and Control Outputs
values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction
temperature range for operation, -40 to +125°C. (Notes 2, 7, 8, 9)
Unless otherwise noted, V
DD_A, _D
, V
PVDD1,2
, RESETN, ENABLE = 3.6V. Typical
Symbol
V
OL
Parameter
Output low level
Conditions
PWROK, GPOx, SPWI,
I
SINK
≤
1 mA
PWROK, GPOx, I
SOURCE
≤
1 mA
SPWI, I
SOURCE
≤
1 mA
Min
Typ
Max
0.4
Units
V
V
OH
V
OH_PWI
Output high level
V
BAT1
-0.4V
V
O2
-0.4V
V
Output high level, PWI
V
Note 1:
Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation
of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions,
see the Electrical Characteristics tables.
Note 2:
All voltages are with respect to the potential at the GND pin.
Note 3:
The Human body model is a 100 pF capacitor discharged through a 1.5 k
resistor into each pin.
The amount of Absolute Maximum power dissipation allowed for the device depends on the ambient temperature and can be calculated using the formula P =
(TJ – TA)/
θ
JA
, (1) where TJ is the junction temperature, TA is the ambient temperature, and JA is the junction-to-ambient thermal resistance.
Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists, special
care must be paid to thermal dissipation issues in board design.
Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ=150°C (typ.) and disengages at TJ=140°C
(typ.).
www.national.com
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