參數(shù)資料
型號(hào)： LP5527TLX
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 顯示驅(qū)動(dòng)器
英文描述： Tiny LED Driver for Camera Flash and 4 LEDs with I2C Programmability, Connectivity Test and Audio Synchronization
中文描述： LED DISPLAY DRIVER, PBGA30
封裝： 2.5 X 3 MM, 0.60 MM HEIGHT, BGA-30
文件頁(yè)數(shù)： 17/21頁(yè)
文件大?。?/td> 829K
代理商： LP5527TLX
I
2
C Compatible Interface
(Continued)
10
C
b
Bus Free Time between a STOP and a START Condition
Capacitive Load for Each Bus Line
NOTE:
Data guaranteed by design
1.3
10
μs
pF
200
Test Interface
The test bus can be controlled externally or internally. For
the external control, the LP5527 pins V
only need to be
powered. External control is independent on status of NRST
and V
DDIO
pins. T1 is an input and it has an internal 6 k
pull-down resistor. T2 is an output line for the test result with
an internal 200 k
pull-down resistor. When T1 is low, T2 is
always pulled down; when T1 is high, T2 is indicating the
result of the test.
20184019
High Level Schematic Representation of the Test Interface
The device is capable of detecting a defective unit in three
cases:
Production test 1:
The LP5527 is assembled on a
printed wiring board (PWB), but there is no LEDs con-
nected on current sink outputs. An external 4.2V test
voltage is supplied on the V
DD1
and V
DD2
pins, from
which follows that the reset operating mode is entered
with POR. Test pin T1 is pulled high. The chip will send an
acknowledge “1” onto the T2 pin if the chip is in working
order; otherwise T2 stays low (0). Refer to Test Interface
Timing Diagram.
Production test 2:
The LP5527 is assembled on a PWB
with the external components shown in LP5527 Block
Diagram. 4.2V voltage is connected to V
, V
and
FB pins (see the figure above), from which follows that
the reset operating mode is entered with POR. Test pin
T1 is pulled high. The chip will send an acknowledge “1”
onto the T2 pin if the chip is in working order; otherwise
T2 stays low (0). If the ACK is “1”, a repetitive test pattern
“0-1-0-1-0-1-0-1-0-1-0-1” is applied to T1 pin and if the
LED corresponding the pattern (see Test Interface Timing
Diagram) is connected properly T2 gives “1”, otherwise
T2 stays low. The last “1” disengages the test.
Field test:
Build-in self-test through the I
2
C compatible
control interface. The LP5527 is enabled (NSTBY(bit) =
1, EN_BOOST(bit) = 1) and external test pins T1 and T2
are disconnected. The result can be read through the I
2
C
compatible control interface. LED test is enabled by writ-
ing to address 0Ch hex data 01h. Result can be read
from the same address during the next I
2
C cycle. Note:
I
2
C compatible interface clock signal controls the timing
of the test procedure. For that reason the clock signal
frequency should be 50 kHz or less during the build-in
self-test.
L
www.national.com
17
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