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參數(shù)資料
| 型號： | LP5527TLX |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 顯示驅(qū)動器 |
| 英文描述： | Tiny LED Driver for Camera Flash and 4 LEDs with I2C Programmability, Connectivity Test and Audio Synchronization |
| 中文描述： | LED DISPLAY DRIVER, PBGA30 |
| 封裝： | 2.5 X 3 MM, 0.60 MM HEIGHT, BGA-30 |
| 文件頁數(shù)： | 15/21頁 |
| 文件大?。?/td> | 829K |
| 代理商： | LP5527TLX |
I
2
C Compatible Interface
I
2
C SIGNALS
The SCL pin is used for the I
2
C clock and the SDA pin is
used for bidirectional data transfer. Both these signals need
a pull-up resistor according to I
2
C specification. The values
of the pull-up resistors are determined by the capacitance of
the bus (typ.~1.8 k
). Signal timing specifications are
shown in table I
2
C Timing Parameters.
I
2
C DATA VALIDITY
The data on SDA line must be stable during the HIGH period
of the clock signal (SCL). In other words, state of the data
line can only be changed when CLK is LOW.
20184049
I
2
C Signals: Data Validity
I
2
C START AND STOP CONDITIONS
START and STOP bits classify the beginning and the end of
the I
2
C session. START condition is defined as SDA signal
transitioning from HIGH to LOW while SCL line is HIGH.
STOP condition is defined as the SDA transitioning from
LOW to HIGH while SCL is HIGH. The I
2
C master always
generates START and STOP bits. The I
2
C bus is considered
to be busy after START condition and free after STOP con-
dition. During data transmission, I
2
C master can generate
repeated START conditions. First START and repeated
START conditions are equivalent, function-wise.
20184050
I
2
C Start and Stop Conditions
TRANSFERRING DATA
Every byte put on the SDA line must be eight bits long, with
the most significant bit (MSB) being transferred first. Each
byte of data has to be followed by an acknowledge bit. The
acknowledge related clock pulse is generated by the master.
The transmitter releases the SDA line (HIGH) during the
acknowledge clock pulse. The receiver must pull down the
SDA line during the 9
th
clock pulse, signifying an acknowl-
edge. A receiver which has been addressed must generate
an acknowledge after each byte has been received.
After the START condition, the I
2
C master sends a chip
address. This address is seven bits long followed by an
eighth bit which is a data direction bit (R/W). The LP5527
address is 4C hex. For the eighth bit, a “0” indicates a
WRITE and a “1” indicates a READ. The second byte selects
the register to which the data will be written. The third byte
contains data to write to the selected register.
When a READ function is to be accomplished, a WRITE
function must precede the READ function, as shown in the
I
2
C Read Cycle waveform.
20184051
I
2
C Chip Address 4C hex for LP5527
L
www.national.com
15
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