參數資料
型號: LP39542RLX
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 顯示驅動器
英文描述: Zener Diode; Application: Low noise; Pd (mW): 250; Vz (V): 4.9 to 5.3; Condition Iz at Vz (mA): 0.5; C (pF) max: -; Condition VR at C (V):   ESD (kV) min: -; Package: LLD
中文描述: LED DISPLAY DRIVER, PBGA36
封裝: 3 X 3 MM, 0.65 MM HEIGHT, 0.50 MM PITCH, MICRO, SMD-36
文件頁數: 5/58頁
文件大小: 2547K
代理商: LP39542RLX
Electrical Characteristics
(Notes 2, 11)
Limits in standard typeface are for T
J
= 25°C. Limits in
boldface
type apply over the operating ambient temperature range (-30°C
< T
A
< +85°C). Unless otherwise noted, specifications apply to the LP39542 Block Diagram with: V
DD1
= V
DD2
= 3.6V, V
DDIO
= 2.8V,
C
VDD
= C
VDDIO
= 100 nF, C
OUT
= C
IN
= 10 μ
F, C
VDDA
= 1 μ
F, C
REF
= 100 nF, L
1
= 4.7 μ
H, R
FLASH
= 910Ω
, R
RGB
= 5.6 k
Ω
and R
RT
= 82 k
Ω (
Note 12).
Symbol
Parameter
Condition
I
VDD
Standby supply current
(V
DD1
+ V
DD2
)
SCL=H, SDA = H
No-boost supply current
(V
DD1
+ V
DD2
)
EN_BOOST(bit) = L
SCL = H, SDA = H
Audio sync and LEDs OFF
No-load supply current
(V
DD1
+ V
DD2
)
EN_BOOST (bit) = H
SCL = H, SDA = H
Audio sync and LEDs OFF
Autoload OFF
RGB drivers
(V
DD1
+ V
DD2
)
SW mode
WLED drivers
(V
DD1
+ V
DD2
)
Audio synchronization
(V
DD1
+ V
DD2
)
V
DD1,2
= 2.8V
V
DD1,2
= 3.6V
Flash
(V
DD1
+ V
DD2
)
Peak current during flash
I
VDDIO
V
DDIO
Standby Supply
current
SCL = H, SDA = H
I
EXT_LDO
External LDO output
current
(V
DD1
, V
DD2
, V
DDA
)
V
DDA
Output voltage of internal
LDO for analog parts
Min
Typ
1
Max
8
Units
μ
A
NSTBY (bit) = L, NRST (pin) = H
NSTBY (bit) = H,
450
μ
A
NSTBY (bit) = H,
1
mA
CC mode at R1, G1, B1 and R2, G2, B2 set to 15 mA
150
150
500
μ
A
4+2 banks I
OUT
= 25.5 mA per LED
μ
A
Audio sync ON
μ
A
390
700
I(R
FLASH
) = 1 mA
2
mA
NSTBY (bit)=L
1
μ
A
7V tolerant application only
I
BOOST
= 300 mA
6.5
mA
(Note 13)
2.72
-3
2.80
2.88
+3
V
%
Note 1:
Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation
of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions,
see the Electrical Characteristics tables.
Note 2:
All voltages are with respect to the potential at the GND pins.
Note 3:
Battery/Charger voltage should be above 6V no more than 10% of the operational lifetime.
Note 4:
Voltage tolerance of LP39542 above 6.0V relies on fact that V
and V
(2.8V) are available (ON) at all conditions. If V
DD1
and V
DD2
are not available
(ON) at all conditions, National Semiconductor does not guarantee any parameters or reliability for this device.
Note 5:
The total load current of the boost converter in worst-case conditions is limited to 300 mA (min. input and max. output voltage).
Note 6:
Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at T
J
=160°C (typ.) and disengages at
T
J
=140°C (typ.).
Note 7:
For detailed soldering specifications and information, please refer to National Semiconductor Application Note AN1112 : Micro SMD Wafer Level Chip
Scale Package or Application note AN1412: Micro SMDxt Wafer Lever Chip Scale Package
Note 8:
The Human body model is a 100 pF capacitor discharged through a 1.5 k
resistor into each pin.
Note 9:
In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be
derated. Maximum ambient temperature (T
A-MAX
) is dependent on the maximum operating junction temperature (T
= 125°C), the maximum power
dissipation of the device in the application (P
), and the junction-to ambient thermal resistance of the part/package in the application (
θ
JA
), as given by the
following equation: T
A-MAX
= T
J-MAX-OP
– (θ
JA
× P
D-MAX
).
Note 10:
Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists,
special care must be paid to thermal dissipation issues in board design.
Note 11:
Min and Max limits are guaranteed by design, test, or statistical analysis. Typical numbers are not guaranteed, but do represent the most likely norm.
Note 12:
Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics.
Note 13:
V
DDA
output is not recommended for external use.
5
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