參數(shù)資料
型號: LP3950SL
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 顯示驅動器
英文描述: Color LED Driver with Audio Synchronizer
中文描述: LED DISPLAY DRIVER, QCC32
封裝: 4.50 X 5.50 MM, 0.80 MM HEIGHT, 0.50 MM PITCH, CSP-32
文件頁數(shù): 8/31頁
文件大?。?/td> 1085K
代理商: LP3950SL
Logic Interface Characteristics
(Continued)
(1.80V
V
V
V). Limits in standard typeface are for T
J
= +25C. Limits in
boldface
type apply over the operating
ambient temperature range (40C
T
A
+85C).
Symbol
Parameter
Conditions
LOGIC INPUTS DME, AMODE (Internal pull down 1 M
)
I
I
Logic Input Current
Min
Typ
Max
Units
1.0
6.0
μA
Logic Interface Characteristics, Low I/O Voltage
(1.65V
V
DDIO
<
1.80V) . I
2
C compatible interface only.
Symbol
Parameter
LOGIC INPUTS SCL, PWM_LED, IF_SEL
V
IL
Input Low Level
V
IH
Input High Level
I
I
Logic Input Current
f
SCL
Clock Frequency
I
2
C Mode
LOGIC I/O SDA
V
OL
Output Low Level
I
SDA
= 3.0 mA
LOGIC INPUTS DME, AMODE (Internal pull down 1 M
)
V
IL
Input Low Level
V
IH
Input High Level
I
I
Logic Input Current
Conditions
Min
Typ
Max
Units
0.35
V
V
μA
kHz
V
DDIO
0.35
1.0
1.0
200
0.3
0.5
V
0.35
V
V
μA
V
DDIO
0.35
1.0
6.0
Logic Input NRST Characteristics
(1.65V
V
DDIO
V
DD1,2
V).
Symbol
Parameter
V
IL
Input Low Level
V
IH
Input High Level
I
I
Logic Input Current
t
NRST
Reset Pulse Width
Conditions
Min
Typ
Max
0.5
Units
V
V
μA
1.3
1.0
1.0
Note: Guaranteed by
design
10
μs
Control Interface
The LP3950 supports three different interface modes:
1) SPI interface (4 wire, serial)
2) I
2
C compatible interface (2 wire, serial)
3) Direct enable (2 wire, enable lines)
User can define the serial interface by the IF_SEL pin. The
following table shows the pin configuration for both interface
modes. Note that the pin configurations will be based on the
status of the IF_SEL pin.
IF_SEL
HIGH
Interface
Pin Configuration
Comment
SPI
SCK
SI
SO
SS
SCL
SDA
SI
SO
(clock)
(data in)
(data out)
(chip select)
(clock)
(data in/out)
(I
2
address)
(NC)
LOW
I
2
C Compatible
Use pull up resistor for SCL.
Use pull up resistor for SDA.
SI HIGH
address is 51’h;
SI LOW
address is 50’h;
Unused pin SO can be left unconnected.
SPI Interface
The transmission consists of 16-bit write and read cycles.
One cycle consists of seven address bits, one read/write
(R/W) bit and eight data bits. R/W bit high state defines a
write cycle and low defines a read cycle. SO output is
normally in high-impedance state and it is active only during
when data is sent out during a read cycle. A pull-up or
pull-down resistor may be needed for SO line if a floating
logic signal can cause unintended current consumption in
the circuitry.
The address and data are transmitted Most Significant Byte
(MSB) first. The Slave Select signal (SS) must be low during
the cycle transmission. SS resets the interface when high
L
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