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參數(shù)資料
| 型號： | LP3950SL |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 顯示驅(qū)動器 |
| 英文描述： | Color LED Driver with Audio Synchronizer |
| 中文描述： | LED DISPLAY DRIVER, QCC32 |
| 封裝： | 4.50 X 5.50 MM, 0.80 MM HEIGHT, 0.50 MM PITCH, CSP-32 |
| 文件頁數(shù)： | 10/31頁 |
| 文件大?。?/td> | 1085K |
| 代理商： | LP3950SL |
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SPI Timing Parameters
V
DD1
= V
DD2
= V
DDA
= 2.70V to 2.90V, V
DDIO
= 1.80V to V
DD1,2
V
Symbol
Parameter
Limit
Units
Min
80
40
40
40
40
0
20
Max
1
2
3
4
5
6
7
8
9
10
11
12
Cycle Time
Enable Lead Time
Enable Lag Time
Clock Low Time
Clock High Time
Data Setup Time
Data Hold Time
Data Access Time
Output Disable Time
Output Data Valid
Output Data Hold Time
SS Inactive Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
27
27
37
0
15
Note:
Data guaranteed by design.
I
2
C Compatible Interface
I
2
C SIGNALS
In I
2
C compatible mode, the LP3950 pin SCL is used for the
I
2
C clock and the SDA pin is used for the I
2
C data. Both
these signals need a pull-up resistor according to I
2
C speci-
fication. The values of the pull-up resistors are determined
by the capacitance of the bus (typ.
A
1.8k). Signal timing
specifications are shown in
Table I
2
C Timing Parameters
.
Unused pin SO can be left unconnected and pin SI must be
connected to V
or GND (address selector). Maximum bit
rate is 400 kbit/s (V
1.80V to V
DD1,2
V). I
2
C compatible
interface can be used down to 1.65 V
DDIO
with maximum bit
rate of 200 kbit/s.
I
2
C DATA VALIDITY
The data on the SDA line must be stable during the HIGH
period of the clock signal (SCL). In other words, state of the
data line can only be changed when CLK is LOW.
I
2
C START AND STOP CONDITIONS
START and STOP bits classify the beginning and the end of
the I
2
C session. START condition is defined as SDA signal
transition from HIGH to LOW while SCL line is HIGH. STOP
condition is defined as the SDAtransition from LOW to HIGH
while SCL is HIGH. The I
2
C master always generates
START and STOP bits. The I
2
C bus is considered to be busy
after START condition and free after STOP condition. During
data transmission, the I
2
C master can generate repeated
START conditions. First START and repeated START condi-
tions are equivalent, function-wise.
20129310
FIGURE 5. I
2
C Signals: Data Validity
L
www.national.com
10
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LP3950SL/CSP1 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Texas Instruments 功能描述: |
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| LP3950SLX | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Color LED Driver with Audio Synchronizer |
| LP3950SLX/NOPB | 功能描述:IC LED DRVR WHITE BCKLGT 32-TSCP RoHS:是 類別:集成電路 (IC) >> PMIC - LED 驅(qū)動器 系列:PowerWise® 標(biāo)準(zhǔn)包裝:1 系列:- 恒定電流:- 恒定電壓:- 拓?fù)?PWM，切換式電容器（充電泵） 輸出數(shù):1 內(nèi)部驅(qū)動器:是 類型 - 主要:背光 類型 - 次要:白色 LED 頻率:642kHz 電源電壓:2.7 V ~ 5.5 V 輸出電壓:5V 安裝類型:表面貼裝 封裝/外殼:10-VFDFN 裸露焊盤 供應(yīng)商設(shè)備封裝:10-VSON 包裝:剪切帶 (CT) 工作溫度:-30°C ~ 85°C 產(chǎn)品目錄頁面:1371 (CN2011-ZH PDF) 其它名稱:BD1603NUV-E2CT |
| LP3952 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:6-Channel Color LED Driver with Audio Synchronization |
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