參數(shù)資料
型號: LP3928TL-1828
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 模擬信號調(diào)理
英文描述: SUBMINIATURE PC BOARD RELAY
中文描述: SPECIALTY ANALOG CIRCUIT, PBGA16
封裝: MICRO SMD, 16 PIN
文件頁數(shù): 8/11頁
文件大?。?/td> 240K
代理商: LP3928TL-1828
Note 16:
This is the static current consumption from V
CCA
for the part common to the channels.
Note 17:
Only I
CCBTOTAL
for DIR1=DIR2=DIR3=H and I
CCATOTAL
for DIR1=DIR2=DIR3=L will be tested in production.
Calculation example:
assuming DIR1=H, DIR2=L, DIR3=L, then the typical I
CCB
current will be:
I
CCBTOTAL
= I
BCOM
+ I
CHA
B
+ 2
*
I
CHB
A
= 450 μA + 530 μA + 2
*
2 μA = 984 μA
The typical I
CCA
current is:
I
CCATOTAL
= I
A
= 90 μA.
Note 18:
This is the time it takes either to switch the level shifter on or off, or the time it takes to turn the latch by-pass on/off.
Note 19:
This is the time it takes to switch the direction of the level shifter. After this time a signal can be applied on the new input. For the B
A direction, if EN2=1,
the latch set-up time has to be considered separately.
Note 20:
The output voltage changes slightly with line voltage. An increase in the line voltage results in a slight increase in the output voltage and vice versa.
Note 21:
The output voltage changes slightly with load current. An increase in the load current results in a slight decrease in the output voltage and vice versa.
Note 22:
Dropout voltage is the input-to-output voltage difference at which the output voltage is 100 mV below its normal value. This specification does not apply
for input voltages below 2.7V.
Note 23:
Turn-on time is that between the enable input just exceeding V
IH
and the output voltage just reaching 95% of its nominal value.
Note 24:
Range of capacitor values for which the device will remain stable. This electrical specification is guaranteed by design.
Note 25:
Range of capacitor ESR values for which the device will remain stable. This electrical specification is guaranteed by design.
Note 26:
The built-in thermal shut-down of the LDO is also used to put all Ai and Bi outputs in tristate mode.
Note 27:
Additional information on lead temperature and pad temperature can be found in National Semiconductor Application Note (AN-1112).
Note 28:
Unused inputs must be terminated.
Note 29:
This electrical specification is guaranteed by design.
Typical Performance Characteristics
C
VCCB
= 1 μF, V
BAT
= 3.3V, V
CCA
= 1.8V, T
A
= 25C.
Level Shifter Propagation Delay A
B
Unless otherwise specified: C
VBAT
= 1 μF, C
VCCA
= 1 μF,
Level Shifter Propagation Delay B
A
20039109
20039110
20039106
FIGURE 1. Output AC Line Regulation
20039107
FIGURE 2. PSRR Input Perturbation
L
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