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參數資料
| 型號： | LP2975AIMMX-3.3/NOPB |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 模擬信號調理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PDSO8 |
| 封裝： | MINI, SOP-8 |
| 文件頁數： | 2/20頁 |
| 文件大?。?/td> | 1135K |
| 代理商： | LP2975AIMMX-3.3/NOPB |
Reference Designs (Continued)
The load resistor is connected to the regulator output using a
switch so that the load current increases from 0 to 0.5A
abruptly. The change in output voltage is shown in the scope
photo (the vertical scale is 20 mV/division and the horizontal
scale is 50 s/division). The regulator nominal output (3V) is
located on the center line of the photo. A maximum change
of about 50 mV is shown.
10003438
Transient Response for 0–0.5A Load Step
Minimizing C
OUT
It is often desirable to decrease the value of C
OUT to save
cost and reduce size. The design guidelines suggest select-
ing C
OUT to set the first pole
≤ 200 Hz (see later section
Output Capacitor), but this is not an absolute requirement in
all cases.
The effect of reducing C
OUT is to decrease phase margin. As
phase margin is decreased, the output ringing will increase
when a load step is applied to the output. Eventually, if C
OUT
is made small enough, the regulator will oscillate.
To demonstrate these effects, the value of C
OUT in reference
design #2 is halved by removing one of the two 68 F output
capacitors and the transient response test is repeated (see
photo below). The total overshoot increases from 50 mV to
about 75 mV, and the second “ring” on the transient is
noticeably larger.
10003439
Transient Response with Output Capacitor Halved
The design is next tested with only a 4.7 F output capacitor
(see scope photo below). Observe that the vertical scale has
been increased to 100 mV/division to accommodate the
250 mV undershoot. More important is the severe ringing
as the transient decays. Most designers would recognize
this immediately as the warning sign of a marginally stable
design.
10003440
Transient Response with Only 4.7 F Output Cap
The reason this design is marginally stable is that the 4.7 F
output capacitor (along with the 6
output load) sets the pole
f
p at 5 kHz. Analysis shows that the unity-gain frequency of
the loop is increased to about 100 kHz, allowing the FET’s
gate capacitance pole f
pg to cause significant phase shift
before the loop gain goes below unity. Also, because of the
low output voltage, the feedforward capacitor provides less
than 10 of positive phase shift. For good stability, the output
capcitor needs to be larger than 4.7 F.
For detailed information on stability and phase margin, see
the Application Hints section.
LP2975
www.national.com
10
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相關代理商/技術參數 |
參數描述 |
|---|---|
| LP2975AIMMX-5.0 | 功能描述:低壓差穩(wěn)壓器 - LDO RoHS:否 制造商:Texas Instruments 最大輸入電壓:36 V 輸出電壓:1.4 V to 20.5 V 回動電壓（最大值）:307 mV 輸出電流:1 A 負載調節(jié):0.3 % 輸出端數量: 輸出類型:Fixed 最大工作溫度:+ 125 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-20 |
| LP2975AIMMX-5.0/NOPB | 功能描述:低壓差穩(wěn)壓器 - LDO RoHS:否 制造商:Texas Instruments 最大輸入電壓:36 V 輸出電壓:1.4 V to 20.5 V 回動電壓（最大值）:307 mV 輸出電流:1 A 負載調節(jié):0.3 % 輸出端數量: 輸出類型:Fixed 最大工作溫度:+ 125 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-20 |
| LP2975IMM-12/NOPB | 功能描述:IC REG CTRLR SGL 12V 8-MSOP RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - 線性晶體管驅動器 系列:- 產品培訓模塊:More Information on LDOs 標準包裝:2,500 系列:- 類型:正，固定式 輸出數:2 輸出電壓:2.8V，3.3V 電流 - 電源:12mA 輸入電壓:5 V ~ 22 V 工作溫度:0°C ~ 70°C 封裝/外殼:16-SOIC（0.154"，3.90mm 寬） 供應商設備封裝:16-SOIC 包裝:帶卷 (TR) |
| LP2975IMM-3.3 | 功能描述:低壓差穩(wěn)壓器 - LDO RoHS:否 制造商:Texas Instruments 最大輸入電壓:36 V 輸出電壓:1.4 V to 20.5 V 回動電壓（最大值）:307 mV 輸出電流:1 A 負載調節(jié):0.3 % 輸出端數量: 輸出類型:Fixed 最大工作溫度:+ 125 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-20 |
| LP2975IMM-3.3/NOPB | 功能描述:低壓差穩(wěn)壓器 - LDO RoHS:否 制造商:Texas Instruments 最大輸入電壓:36 V 輸出電壓:1.4 V to 20.5 V 回動電壓（最大值）:307 mV 輸出電流:1 A 負載調節(jié):0.3 % 輸出端數量: 輸出類型:Fixed 最大工作溫度:+ 125 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-20 |
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