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LNBEH21
8/22
RECEIVED DATA (I
2
C bus READ MODE)
The LNBEH21 can provide to the Master a copy of the SYSTEM REGISTER information via I
2
C bus in
read mode. The read mode is Master activated by sending the chip address with R/W bit set to 1. At the
following master generated clocks bits, the LNBEH21 issues a byte on the SDA data bus line (MSB
transmitted first).
At the ninth clock bit the MCU master can:
- acknowledge the reception, starting in this way the transmission of another byte from the LNBEH21;
- no acknowledge, stopping the read mode communication.
While the whole register is read back by the μP, only the two read-only bits OLF and OTF convey
diagnostic informations about the LNBEH21
Values are typical unless otherwise specified
POWER-ON I
2
C INTERFACE RESET
The I
2
C interface built in the LNBEH21 is automatically reset at power-on. As long as the V
CC
stays below
the UnderVoltage Lockout threshold (6.7V typ.), the interface will not respond to any I
2
C command and
the System Register (SR) is initialized to all zeroes, thus keeping the power blocks disabled. Once the
V
CC
rises above 7.3V typ, the I
2
C interface becomes operative and the SR can be configured by the main
μP. This is due to 500mV of hysteresis provided in the UVL threshold to avoid false retriggering of the
Power-On reset circuit.
ADDRESS PIN
Connecting this pin to GND the Chip I
2
C interface address is 0001000, but, it is possible to choice among
4 different addresses simply setting this pin at 4 fixed voltage levels (see table on page 11).
COMMUNICATION MODE SELECTION
I
2
C OM bit (Operating Mode selection bit)
The LNBEH21 can work either in DiSEqC
TM
mode or in 13/18V Control Word mode; the selection of the
communication mode is achieved through the dedicated I
2
C OM bit that must be respectively set to LOW
or to HIGH. Depending on the communication mode selection (OM bit state) the I
2
C VOM bit and the TEN/
VSEL pin (#14) operation are switched between two different functions:
VOM bit and TEN/VSEL pin functions with OM=0 (DiSEqC
TM
mode).
- The TEN/VSEL pin controls the 22KHz bursting code, by enabling the internal 22KHz tone generator, to
allow immediate DiSEqC
TM
data encoding.
- In DiSEqC
TM
mode, the VOM I
2
C bit controls simultaneously the post-regulator output voltage (V
OUT
)
and the DC/DC converter output voltage (V
UP
). The VOM bit function is to select the LNB output voltage
to 13.25V or 19.5V respectively if VOM=0 or VOM=1 (14.25V or 20.5V if LLC=1) and V
UP
is set to
V
OUT
+2.2V typ., according to DiSEqC section in the Truth Table on page 11;
PCL
TTX
OM
LLC
VOM
EN
OTF
OLF
Function
These bits are read exactly the same as
they were left after last write operation
0
1
T
J
<135°C, normal operation
T
J
>150°C, power block disabled
I
OUT
<I
OMAX
, normal operation
I
OUT
>I
OMAX
, overload protection triggered
0
1