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LNBEH21
14/22
THERMAL DESIGN NOTES
During normal operation, this device dissipates some power. The power dissipation depends on the
selected communication mode (DiSEqC or 13/18 control word communication).
When the device is used in DiSEqC mode, at maximum rated output current (750mA), the voltage drop on
the linear regulator lead to a total dissipated power that is about 1.65W.
If the control word communication mode is selected, at maximum rated current of 450mA, the total power
dissipated is about 1W. By the way, during the 13/18V pulses code transmission (OM=VOM=1) the
average power dissipation is higher than 1W because, in this case, before to start sending the 13/18V
pulses code, the V
UP
voltage must be forced in steady state at 21.7V by VOM=1, (22.7V if LLC=1) in order
to ensure the proper code transition rise and fall timing while the V
OUT
voltage is continuously switched
between 13V and 18V; this means that, in the 13V half period the peak of power dissipation is about 3.8W
typ. (@ Iout=450mA max.). Obviously this is the peak power dissipation as the average value during the
code transmission has to be calculated taking into account the 0/1 bits combination.
The heat generated requires a suitable heatsink to keep the junction temperature below the
overtemperature protection threshold. Assuming a 45°C temperature inside the Set-Top-Box case and a
max continuos power dissipation of 1.65W, the total R
thj-amb
has to be less than 48°C/W.
While this can be easily achieved using a through-hole power package that can be attached to a small
heatsink or to the metallic frame of the receiver, a surface mount power package must rely on PCB
solutions whose thermal efficiency is often limited. The simplest solution is to use a large, continuous
copper area of the pcb ground layer to dissipate the heat coming from the IC body by mean the ground
exposed pad present on the bottom side of the PSO-20 package.
Given for the PSO-20 an R
thj-case
equal to 2°C/W, a maximum of 46°C/W are left to the PCB heatsink.
This figure is achieved if a minimum of 6.5cm
2
copper area is placed just below the IC body. This area can
be the inner GND layer of a multi-layer PCB, or, in a dual layer PCB, an unbroken GND area even on the
opposite side where the IC is placed. In figure 9, is shown a suggested layout for the PSO-20 package
with a dual layer PCB, where the IC exposed pad connected to GND and the square dissipating area are
thermally connected through 32 vias holes, filled by solder. This arrangement, when L=25mm, achieves
an R
thc-a
of about 32°C/W.
Different layouts are possible, too. Basic principles, however, suggest to keep the IC and its ground
exposed pad approximately in the middle of the dissipating area; to provide as many vias as possible; to
design a dissipating area having a shape as square as possible and not interrupted by other copper
traces.
Figure 9: PowerSO-20 Suggested Pcb Heatsink Layout