參數(shù)資料
型號: LMX9830SMX
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 通信及網(wǎng)絡
英文描述: BluetoothTM Serial Port Module
中文描述: SPECIALTY TELECOM CIRCUIT, PBGA60
封裝: 9 X 6 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, PLASTIC, FBGA-60
文件頁數(shù): 15/46頁
文件大?。?/td> 664K
代理商: LMX9830SMX
15
www.national.com
L
8.0 Functional Description
(Continued)
.
8.4 AUXILIARY PORTS
8.4.1 RESET#
There are two reset inputs: RESET_RA# for the radio and
RESET_BB# for the baseband. Both are active low.
There is also a reset output, B_RESET_RA# (Buffered
Radio Reset) active low. This output follows input
RESET_RA#.
When
B_RESET_RA# stays low until the clock has started.
RESET_RA#
is
released,
going
high,
Please see Section 8.5 "System Power Up" on page 15 for
details.
8.4.2 General Purpose I/Os
The LMX9830 offers 3 pins which either can be used as
indication and configuration pins or can be used for Gen-
eral Purpose functionality. The selection is made out of set-
tings derived out of the power up sequence.
In General Purpose configuration the pins are controlled
hardware specific commands giving the ability to set the
direction, set them to high or low or enable a weak pull-up.
In alternate function the pins have pre-defined indication
functionality. Please see Table 14 on page 15 for a descrip-
tion on the alternate indication functionality.
8.5 SYSTEM POWER UP
In order to correctly power-up the LMX9830 the following
sequence is recommended to be performed:
Apply VCC_IO and VCC to the LMX9830.
The
RESET_RA#
should
RESET_BB# should be driven high at a recommended
time of 1ms after the LMX9830 voltage rails are high. The
LMX9830 is properly reset.
Please see timing diagram, Figure 9 on page 16.
be
driven
high.
Then
Table 13. Audio path configuration
Audio setting
Interface
Freq
Format
AAI Bit
Clock
AAI Frame
Clock
AAI Frame Sync
Pulse Length
OKI
MSM7717
Advanced audio
interface
ANY
1
8-bit log PCM
(a-law only)
480 KHz
8 KHz
14 Bits
Motorola
MC145483
2
Advanced audio
interface
13-bit linear
480 KHz
8 KHz
13 Bits
OKI
MSM7717
Advanced audio
interface
13MHz
8-bit log PCM
(a-law only)
520 KHz
8 KHz
14 Bits
Motorola
MC145483
3
Advanced audio
interface
13-bit linear
520 KHz
8 KHz
13 Bits
Winbond
W681310
Advanced audio
interface
13MHz
8 bit log PCM
A-law and u-law
520 KHz
8 KHz
14 Bits
Winbond
W681360
Advanced audio
interface
13MHz
13-bit linear
520 KHz
8 KHz
13 Bits
PCM slave
4
Advanced audio
interface
ANY
1
8/16 bits
128 - 1024
KHz
8 KHz
8/16 Bits
1.
2.
For supported frequencies see Table 22 on page 24
Due to internal clock divider limitations the optimum of 512KHz, 8KHz can not be reached. The values are set to the
best possible values. The clock mismatch does not result in any discernible loss in audio quality.
Due to internal clock divider limitations the optimum of 512KHz, 8KHz can not be reached. The values are set to the
best possible values. The clock mismatch does not result in any discernible loss in audio quality.
In PCM slave mode, parameters are stored in NVS. Bit clock and frame clock must be generated by the host interface.
3.
4.
PCM slave configuration example:
PCM slave uses the slot 0, 1 slot per frame, 16 bit linear mode, long frame sync, normal
frame sync. In this case, 0x03E0 should be stored in NVS. See “LMX9830 Software User’s Guide” for more details.
Table 14. Alternate GPIO pin configuration
Pin
Description
OP4/PG4
Operation Mode pin to configure Trans-
port Layer settings during boot-up
PG6
GPIO
PG7
RF Traffic indication
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