參數(shù)資料
型號(hào): LMX9830SM
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 通信及網(wǎng)絡(luò)
英文描述: BluetoothTM Serial Port Module
中文描述: SPECIALTY TELECOM CIRCUIT, PBGA60
封裝: 9 X 6 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, PLASTIC, FBGA-60
文件頁數(shù): 5/46頁
文件大?。?/td> 664K
代理商: LMX9830SM
5
www.national.com
L
6.0 Pad Description
(Continued)
MDODI
1
D1
I/O
SPI Master Out Slave In
OP6/SCL/MSK
C1
OP6
: I
SCL/MSK
: I/O
See Table 17 on
page 17
OP6
: Pin checked during Startup Sequence for con-
figuration option
SCL
: ACCESS.Bus Clock
MSK
: SPI Shift
OP7/SDA/MDID
O
D4
OP7
: I
SDA/MDI
DO
: I/O
See Table 17 on
page 17
OP7
: Pin checked during Startup Sequence for con-
figuration option
SDA
: ACCESS.Bus Serial Data
MDIDO
: SPI Master In Slave Out
OP3/MWCS#
D3
I
See Table 17 on
page 17 and
Table 18 on page
19
OP3
: Pin checked during Startup Sequence for con-
figuration option
MWCS#
: SPI Slave Select Input (active low)
OP4/PG4
D6
OP4
: I
PG4
: I/O
See Table 17 on
page 17 and
Table 18 on page
19
OP4
: Pin checked during Startup Sequence for con-
figuration option
PG4
: GPIO
OP5
F4
I/O
See Table 17 on
page 17 and
Table 18 on page
19
OP5
: Pin checked during Startup Sequence for con-
figuration option
SCLK
F1
I/O
Audio PCM Interface Clock
SFS
F2
I/O
Audio PCM Interface Frame Synchronization
SRD
F3
I
Audio PCM Interface Receive Data Input
STD
E3
O
Audio PCM Interface Transmit Data Output
XOSCEN
A6
O
Clock Request. Toggles with X2 (LP0) crystal
enable/disable
PG6
A7
I/O
GPIO
PG7
D2
I/O
GPIO - Default setup RF traffic LED indication
CTS#
2
C2
I
GND (
if not
used
)
Host Serial Port Clear To Send (active low)
RXD
B3
I
Host Serial Port Receive Data
RTS#
3
B1
O
NC (
if not used
)
Host Serial Port Request To Send (active low)
TXD
C3
O
Host Serial Port Transmit Data
RDY#
A4
O
NC
JTAG Ready Output (active low)
TCK
B4
I
NC
JTAG Test Clock Input
TDI
B5
I
NC
JTAG Test Data Input
TDO
D5
O
NC
JTAG Test Data Output
TMS
A5
I
NC
JTAG Test Mode Select Input
VCO_OUT
F8
O
Charge Pump Output, connect to Loop filter
VCO_IN
F9
I
VCO Tuning Input, feedback from Loop filter
ANT
D10
I/O
RF Antenna 50 ohm Nominal Impedance
VCC_PLL
F6
O
1.8V Core Logic Power Supply Output
VCC_CORE
C5
O
1.8V Voltage Regulator Output
Table 2. Pin Description
Pad Name
Pad
Location
Type
Default Layout
Description
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