參數(shù)資料
型號(hào)： LMX9830SM
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類(lèi)： 通信及網(wǎng)絡(luò)
英文描述： BluetoothTM Serial Port Module
中文描述： SPECIALTY TELECOM CIRCUIT, PBGA60
封裝： 9 X 6 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, PLASTIC, FBGA-60
文件頁(yè)數(shù)： 20/46頁(yè)
文件大?。?/td> 664K
代理商： LMX9830SM
www.national.com
20
L
9.0 Digital Smart Radio
(Continued)
8.7 USING AN EXTERNAL EEPROM FOR NON-
VOLATILE DATA
The LMX9830 offers two interfaces to connect to external
memory. Depending on the EEPROM used, the interface is
activated by setting the correct option pins during start up.
See Table 17 on page 17 for the option pin settings.
The external memory is used to store mandatory parame-
ters like the BD_Address as well as many optional parame-
ters like Link Keys or even User data.
The NVM is organized with fixed addresses for the parame-
ters. Because of that the EEPROM can be preprogrammed
with default parameters in manufacturing. Refer to "Opera-
tion Parameters Stored in LMX9830" for the organization of
the NVS map.
In case the external memory is empty on first startup the
LMX9830 will behave as like no memory is connected. (See
Section 8.6.3 "Startup Without External PROM Available"
on page 17). During the startup process parameters can be
written directly to the EEPROM to be available after next
bootup. On first bootup, the EEPROM will be automatically
programmed to default values, including the UART speed of
9600 BPS. Patches supplied over the TL will be stored au-
tomatically into the EEPROM.
9.0 Digital Smart Radio
9.1 FUNCTIONAL DESCRIPTION
The integrated Digital Smart Radio utilizes a heterodyne re-
ceiver architecture with a low intermediate frequency (2
MHz) such that the intermediate frequency filters can be in-
tegrated on chip. The receiver consists of a low-noise am-
plifier (LNA) followed by two mixers. The intermediate
frequency signal processing blocks consist of a poly-phase
bandpass filter (BPF), two hard-limiters (LIM), a frequency
discriminator (DET), and a post-detection filter (PDF). The
received signal level is detected by a received signal
strength indicator (RSSI).
The received frequency equals the local oscillator frequen-
cy (fLO) plus the intermediate frequency (fIF):
fRF = fLO + fIF (supradyne).
The radio includes a synthesizer consisting of a phase de-
tector, a charge pump, an (off-chip) loop-filter, an RF-fre-
quency divider, and a voltage controlled oscillator (VCO).
The transmitter utilizes IQ-modulation with bit-stream data
that is gaussian filtered. Other blocks included in the trans-
mitter are a VCO buffer and a power amplifier (PA).
9.2 RECEIVER FRONT-END
The receiver front-end consists of a low-noise amplifier
(LNA) followed by two mixers and two low-pass filters for the
I- and Q-channels.
The intermediate frequency (IF) part of the receiver front-
end consists of two IF amplifiers that receive input signals
from the mixers, delivering balanced I- and Q-signals to the
poly-phase bandpass filter. The poly-phase bandpass filter
is directly followed by two hard-limiters that together gener-
ate an AD-converted RSSI signal.
9.2.1 Poly-Phase Bandpass Filter
The purpose of the IF bandpass filter is to reject noise and
spurious (mainly adjacent channel) interference that would
otherwise enter the hard limiting stage. In addition, it takes
care of the image rejection.
The bandpass filter uses both the I- and Q-signals from the
mixers. The out-of-band suppression should be higher than
40 dB (f<1 MHz, f>3 MHz). The bandpass filter is tuned over
process spread and temperature variations by the autotuner
circuitry. A 5th order Butterworth filter is used.
9.2.2 Hard-Limiter and RSSI
The I- and Q-outputs of the bandpass filter are each fol-
lowed by a hard-limiter. The hard-limiter has its own refer-
ence current. The RSSI (Received Signal Strength
Indicator) measures the level of the RF input signal.
The RSSI is generated by piece-wise linear approximation
of the level of the RF signal. The RSSI has a mV/dB scale,
and an analog-to-digital converter for processing by the
baseband circuit. The input RF power is converted to a 5-bit
value. The RSSI value is then proportional to the input pow-
er (in dBm).
The digital output from the ADC is sampled on the BPK-
TCTL signal low-to-high transition.
9.3 RECEIVER BACK-END
The hard-limiters are followed by a two frequency discrimi-
nators. The I-frequency discriminator uses the 90× phase-
shifted signal from the Q-path, while the Q-discriminator
uses the 90× phase-shifted signal from the I-path. A poly-
phase bandpass filter performs the required phase shifting.
The output signals of the I- and Q-discriminator are sub-
stracted and filtered by a low-pass filter. An equalizer is add-
ed to improve the eye-pattern for 101010 patterns.
After equalization, a dynamic AFC (automatic frequency off-
set compensation) circuit and slicer extract the RX_DATA
from the analog data pattern. It is expected that the Eb/No
of the demodulator is approximately 17 dB.
9.3.1 Frequency Discriminator
The frequency discriminator gets its input signals from the
limiter. A defined signal level (independent of the power
supply voltage) is needed to obtain the input signal. Both in-
puts of the frequency discriminator have limiting circuits to
optimize performance. The bandpass filter in the frequency
discriminator is tuned by the autotuning circuitry.
9.3.2 Post-Detection Filter and Equalizer
The output signals of the FM discriminator first go through a
post-detection filter and then through an equalizer. Both the
post-detection filter and equalizer are tuned to the proper
frequency by the autotuning circuitry. The post-detection fil-
ter is a low-pass filter intended to suppress all remaining
spurious signals, such as the second harmonic (4 MHz)
from the FM detector and noise generated after the limiter.
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