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參數(shù)資料
| 型號： | LMX2487ESQX |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | 7.5 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 3.0 GHz Integer PLL |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 7500 MHz, PQCC24 |
| 封裝： | 4 X 4 MM, 0.80 MM HEIGHT, LLP-24 |
| 文件頁數(shù)： | 18/38頁 |
| 文件大?。?/td> | 419K |
| 代理商： | LMX2487ESQX |
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30013970
Frequency Input Pin
DC Blocking Capacitor
Corresponding
Counter
RF_R / 2
RF_N / 2
Default Counter Value
MUX Value
OSCin
FinRF
1000 pF
50
14
15
100 pF// 1000 pF
502 + 2097150 /
4194301
534
50
FinIF
OSCin
100 pF
1000 pF
IF_N / 2
IF_R / 2
13
12
Sensitivity Measurement Procedure
Sensitivity is defined as the power level limits beyond which the output of the counter being tested is off by 1 Hz or more of its
expected value. It is typically measured over frequency, voltage, and temperature. In order to test sensitivity, the MUX[3:0] word
is programmed to the appropriate value. The counter value is then programmed to a fixed value and a frequency counter is set to
monitor the frequency of this pin. The expected frequency at the Ftest/LD pin should be the signal generator frequency divided by
twice the corresponding counter value. The factor of two comes in because the LMX2487E has a flip-flop which divides this
frequency by two to make the duty cycle 50% in order to make it easier to read with the frequency counter. The frequency counter
input impedance should be set to high impedance. In order to perform the measurement, the temperature, frequency, and voltage
is set to a fixed value and the power level of the signal is varied. Note that the power level at the part is assumed to be 4 dB less
than the signal generator power level. This accounts for 1 dB for cable losses and 3 dB for the pad. The power level range where
the frequency is correct at the Ftest/LD pin to within 1 Hz accuracy is recorded for the sensitivity limits. The temperature, frequency,
and voltage can be varied in order to produce a family of sensitivity curves. Since this is an open-loop test, the charge pump is set
to TRI-STATE and the unused side of the PLL (RF or IF) is powered down when not being tested. For this part, there are actually
four frequency input pins, although there is only one frequency test pin (Ftest/LD). The conditions specific to each pin are shown
in above table.
Note that for the RF N counter, a fourth order fractional modulator is used in 22-bit mode with a fraction of 2097150 / 4194301 is
used. The reason for this long fraction is to test the RF N counter and supporting fractional circuitry as completely as possible.
www.national.com
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LMX2487ESQX/NOPB | 功能描述:鎖相環(huán) - PLL RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| LMX2487SQ | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:3.0 GHz - 6.0 GHz High Performance Delta-Sigma Low Power Dual PLLatinum? Frequency Synthesizers with 3.0 GHz Integer PLL |
| LMX2487SQ/NOPB | 功能描述:鎖相環(huán) - PLL RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| LMX2487SQX | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:3.0 GHz - 6.0 GHz High Performance Delta-Sigma Low Power Dual PLLatinum? Frequency Synthesizers with 3.0 GHz Integer PLL |
| LMX2487SQX/NOPB | 功能描述:鎖相環(huán) - PLL RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
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