- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385492 > LMX2487E (National Semiconductor Corporation) 7.5 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 3.0 GHz Integer PLL PDF資料下載
參數(shù)資料
| 型號： | LMX2487E |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 7.5 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 3.0 GHz Integer PLL |
| 中文描述： | 7.5 GHz的高性能Δ-Σ低功耗雙PLLatinum⑩頻率合成器與整數(shù)的3.0 GHz鎖相環(huán) |
| 文件頁數(shù)： | 31/38頁 |
| 文件大?。?/td> | 419K |
| 代理商： | LMX2487E |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁當前第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁
2.5 R4 REGISTER
This register controls the conditions for the RF PLL in Fastlock.
REGISTER
23
22 21 20 19 18 17 16 15 14 13
12
11
10
9
8
7 6 5 4
3
2
1
0
DATA[19:0]
FM
[1:0]
C3 C2 C1 C0
R4
ATPU
0
1
0
0
0
DITH
[1:0]
0
OSC_
2X
OSC_
OUT
IF_
CPP
RF_
CPP
IF_P
MUX
[3:0]
1
0
0
1
2.5.1 MUX[3:0] Frequency Out & Lock Detect MUX
These bits determine the output state of the Ftest/LD pin.
MUX[3:0]
Output Type
High Impedance
Output Description
Disabled
General purpose output, Logical “High”
State
General purpose output, Logical “Low”
State
RF & IF Digital Lock Detect
RF Digital Lock Detect
IF Digital Lock Detect
RF & IF Analog Lock Detect
RF Analog Lock Detect
IF Analog Lock Detect
RF & IF Analog Lock Detect
RF Analog Lock Detect
IF Analog Lock Detect
IF R Divider divided by 2
IF N Divider divided by 2
RF R Divider divided by 2
RF N Divider divided by 2
0
0
0
0
0
0
0
1
Push-Pull
0
0
1
0
Push-Pull
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
Push-Pull
Push-Pull
Push-Pull
Open Drain
Open Drain
Open Drain
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Push-Pull
2.5.2 IF_P -- IF Prescaler
When this bit is set to 0, the 8/9 prescaler is used. Otherwise the 16/17 prescaler is used.
IF_P
0
1
IF Prescaler
8/9
16/17
Maximum Frequency
800 MHz
800 MHz
2.5.3 RF_CPP -- RF PLL Charge Pump Polarity
RF_CPP
0
1
RF Charge Pump Polarity
Negative
Positive (Default)
2.5.4 IF_CPP -- IF PLL Charge Pump Polarity
For a positive phase detector polarity, which is normally the case, set this bit to 1. Otherwise set this bit for a negative phase
detector polarity.
IF_CPP
0
1
IF Charge Pump Polarity
Negative
Positive
31
www.national.com
L
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LMX2487ESQ | 7.5 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 3.0 GHz Integer PLL |
| LMX2487ESQX | 7.5 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 3.0 GHz Integer PLL |
| LMX2515 | PLLatinum⑩ Frequency Synthesizer System with Integrated VCO |
| LMX2515LQ0701 | PLLatinum⑩ Frequency Synthesizer System with Integrated VCO |
| LMX2515LQ1321 | PLLatinum⑩ Frequency Synthesizer System with Integrated VCO |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LMX2487E-EVM | 功能描述:EVAL MODULE FOR LMX2487 制造商:texas instruments 系列:PLLatinum?? 零件狀態(tài):在售 類型:頻率合成器 頻率:3GHz ~ 7.5GHz 配套使用產(chǎn)品/相關(guān)產(chǎn)品:LMX2487E 所含物品:板 標準包裝:1 |
| LMX2487ESQ | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:7.5 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 3.0 GHz Integer PLL |
| LMX2487ESQ/NOPB | 功能描述:鎖相環(huán) - PLL RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| LMX2487ESQE | 制造商:Texas Instruments 功能描述:PLL, 7.5GHZ, DUAL, DELTA SIGMA, SMD 制造商:Texas Instruments 功能描述:Delta-Sigma LPower Dual PLL,LMX2487ESQE |
| LMX2487ESQE/NOPB | 功能描述:鎖相環(huán) - PLL RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
發(fā)布緊急采購，3分鐘左右您將得到回復。