參數(shù)資料
型號: LMX2487E
廠商: National Semiconductor Corporation
英文描述: 7.5 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 3.0 GHz Integer PLL
中文描述: 7.5 GHz的高性能Δ-Σ低功耗雙PLLatinum⑩頻率合成器與整數(shù)的3.0 GHz鎖相環(huán)
文件頁數(shù): 21/38頁
文件大?。?/td> 419K
代理商: LMX2487E
CE Pin
RF_PD
ATPU
Bit Enabled +
Write to RF
N Counter
X
PLL State
Low
X
Powered Down
(Asynchronous)
Powered Up
Powered Up
Powered Down
( Asynchronous )
High
High
High
X
0
1
Yes
No
No
1.7 DIGITAL LOCK DETECT OPERATION
The RF PLL digital lock detect circuitry compares the differ-
ence between the phase of the inputs of the phase detector
to a RC generated delay of
ε
. To indicate a locked state (Lock
= HIGH) the phase error must be less than the
ε
RC delay for
5 consecutive reference cycles. Once in lock (Lock = HIGH),
the RC delay is changed to approximately
δ
. To indicate an
out of lock state (Lock = LOW), the phase error must become
greater
δ
. The values of
ε
and
δ
are dependent on which PLL
is used and are shown in the table below:
PLL
RF
IF
ε
δ
10 ns
15 ns
20 ns
30 ns
When the PLL is in the power down mode and the Ftest/LD
pin is programmed for the lock detect function, it is forced
LOW. The accuracy of this circuit degrades at higher com-
parison frequencies. To compensate for this, the DIV4 word
should be set to one if the comparison frequency exceeds 20
MHz. The function of this word is to divide the comparison
frequency presented to the lock detect circuit by 4. Note that
if the MUX[3:0] word is set such as to view lock detect for both
PLLs, an unlocked (LOW) condition is shown whenever either
one of the PLLs is determined to be out of lock.
30013904
21
www.national.com
L
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