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參數(shù)資料
| 型號： | LMX2470SLEX |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | 2.6 GHz Delta-Sigma Fractional-N PLL with 800 MHz Integer-N PLL |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 2600 MHz, PQCC24 |
| 封裝： | CSP-24 |
| 文件頁數(shù)： | 31/36頁 |
| 文件大?。?/td> | 453K |
| 代理商： | LMX2470SLEX |
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Programming Description
(Continued)
2.5.3 RF_CSR[1:0] -- RF Cycle Slip Reduction
CSR controls the operation of the Cycle Slip Reduction Circuit. This circuit can be used to reduce the occurrence of phase
detector cycle slips. Note that the Fastlock charge pump current, steady state current, and CSR control are all interrelated. The
table below gives some rough guidelines. In the table below, f
COMP
is the comparison frequency, and BW is the loop bandwidth
of the PLL system. The rough guideline gives an idea of when it makes sense to use this cycle slip reduction based on the
steady-state conditions of the PLL system.
CSR[1:0]
0
1
2
3
CSR State
Disabled
Enabled
Enabled
Enabled
Sample Rate Reduction Factor
1
1/2
1/4
1/16
Rough Guideline
f
COMP
<
100 x BW
100 x BW
<
f
COMP
<
200 x BW
200 x BW
<
f
COMP
<
400 x BW
f
COMP
>
400 x BW
2.6 R5 REGISTER
REGISTER
23
22
21
20
DATA[19:0] ( Except for the RF_N Register, which is [22:0] )
0
0
0
0
0
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
C3
1
C2
0
C1
0
C0
1
R5
0
0
0
IF_TOC[11:0]
2.6.1 IF_TOC[11:0] IF Timeout Counter for Fastlock
The IF_TOC word controls the operation of the IF Fastlock circuitry as well as the function of the FLoutIF output pin. When
IF_TOC is set to a value between 0 and 3, the IF Fastlock circuitry is disabled and the FLoutIF pin operates as a general purpose
CMOS TRI-STATE output. When IF_TOC is set to a value between 4 and 4095, the IF Fastlock mode is enabled and FLoutIF is
utilized as the IF Fastlock output pin. The value programmed into IF_TOC represents the number of phase comparison cycles that
the IF synthesizer will spend in the Fastlock state.
IF_TOC[11:0]
0
1
Fastlock Mode
Disabled
Manual
Fastlock Period [Charge Pump Cycles]
N/A
N/A
FLoutIF Pin Functionality
High Impedance
Logic “0” State
Forces IF charge pump current to 4 mA
Logic “0” State
Logic “1” State
Fastlock
Fastlock
Fastlock
2
3
4
…
Disabled
Disabled
Enabled
Enabled
Enabled
N/A
N/A
5
…
4095
4095
L
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PDF描述 |
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| LMX2485 | 50 MHz - 3.0 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 800 MHz Integer PLL |
| LMX2485E | 50 MHz - 3.0 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 800 MHz Integer PLL |
| LMX2485ESQ | 50 MHz - 3.0 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 800 MHz Integer PLL |
| LMX2485ESQX | 50 MHz - 3.0 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 800 MHz Integer PLL |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LMX2470SLEX/NOPB | 功能描述:鎖相環(huán) - PLL RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| LMX2471 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:3.6 GHz Delta-Sigma Fractional-N PLL with 1.7 GHz Integer-N PLL |
| LMX2471 WAF | 制造商:Texas Instruments 功能描述: |
| LMX2471SLEX | 功能描述:IC PLL LP 3.6GHZ/1.7GHZ 24-CSP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| LMX2471SLEX/NOPB | 制造商:Texas Instruments 功能描述:PLL Dual 250MHz to 3600MHz 24-Pin LAM CSP T/R |
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