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參數(shù)資料
| 型號： | LMX2470SLEX |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | 2.6 GHz Delta-Sigma Fractional-N PLL with 800 MHz Integer-N PLL |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 2600 MHz, PQCC24 |
| 封裝： | CSP-24 |
| 文件頁數(shù)： | 19/36頁 |
| 文件大小： | 453K |
| 代理商： | LMX2470SLEX |
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Functional Description
(Continued)
1.4 DIGITAL LOCK DETECT OPERATION
The RF PLL digital lock detect circuitry compares the differ-
ence between the phase of the inputs of the phase detector
to a RC generated delay of 10 nS. To enter the locked state
(Lock = HIGH) the phase error must be less than the 10nS
RC delay for 5 consecutive reference cycles. Once in lock
(Lock = HIGH), the RC delay is changed to approximately
20nS. To exit the locked state (Lock = LOW), the phase error
must become greater than the 20nS RC delay. When the
PLL is in the power down mode, Lock is forced LOW. For the
RF PLL, the digital lock detect circuitry does not function
reliably for comparison frequencies above 20 MHz.
The IF PLL digital lock detect circuitry works in a very similar
way as the RF PLL digitial lock circuitry, except that it uses a
delay of less than 15 nS for 5 reference cycles to determine
a locked condition and a delay of greater than 30 nS to
determine the IF PLL is unlocked. Note that if the MUX[3:0]
word is set such as to view lock detect for both PLLs, an
unlocked (LOW) condition is shown whenever either one of
the PLLs is determined to be out of lock. A flow chart of the
IF digital lock detect circuitry is shown below.
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PDF描述 |
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| LMX2485 | 50 MHz - 3.0 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 800 MHz Integer PLL |
| LMX2485E | 50 MHz - 3.0 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 800 MHz Integer PLL |
| LMX2485ESQ | 50 MHz - 3.0 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 800 MHz Integer PLL |
| LMX2485ESQX | 50 MHz - 3.0 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 800 MHz Integer PLL |
| LMX2485SQ | 50 MHz - 3.0 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 800 MHz Integer PLL |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| LMX2470SLEX/NOPB | 功能描述:鎖相環(huán) - PLL RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| LMX2471 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:3.6 GHz Delta-Sigma Fractional-N PLL with 1.7 GHz Integer-N PLL |
| LMX2471 WAF | 制造商:Texas Instruments 功能描述: |
| LMX2471SLEX | 功能描述:IC PLL LP 3.6GHZ/1.7GHZ 24-CSP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應商設備封裝:* 包裝:* |
| LMX2471SLEX/NOPB | 制造商:Texas Instruments 功能描述:PLL Dual 250MHz to 3600MHz 24-Pin LAM CSP T/R |
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