參數(shù)資料
型號: LMX2411
廠商: National Semiconductor Corporation
元件分類: 基帶處理器
英文描述: Baseband Processor for Radio Communications
中文描述: 基帶處理器的無線電通信
文件頁數(shù): 6/10頁
文件大?。?/td> 162K
代理商: LMX2411
Functional Description
OVERVIEW
The LMX2411 is a 3V integrated circuit designed to be ca-
pable of regenerating received GMSK data and generating
GMSK transmitter drive signals to meet the specifications of
the Digital European Cordless Telecommunications (DECT)
standard.
The transmit portion of the LMX2411 functions as a pulse
shaper for incoming serial data, delivering a filtered data
stream capable of modulating a VCO. The ROM and sup-
porting logic is designed to create Gaussian filter pulse re-
sponses. The output of the LPF ROM and DAC is the modu-
lating baseband drive signal that is fed to a VCO.
The receiver section of the LMX2411 processes the filtered
data
stream
produced
by
LMX2240). The data stream is compared against a thresh-
old voltage determined by the DC compensation circuit. This
DC compensation circuit allows control over DC drift due to
temperature, frequency drift, component tolerance, and
aging.
a
demodulator
(e.g.,
the
THE TRANSMIT ROM FILTER
The LMX2411 uses a mask-programmable Read-Only
Memory (ROM) look-up table to construct pulse responses
of a Gaussian filter shape. For DECT, this filter is half the
bandwidth of the bit rate (B
b
T
e
0.5). The output of the
ROM addresses a (voltage mode output) digital-to-analog
converter (DAC). The LMX2411 ROM Filter supports three
different system clocks selected by two external pins.
These pins (ROM Sel1 and ROM Sel2) choose the proper
oversampling clock. When the 12x or 16x clock is chosen, a
divide by 2 flip flop is enabled to give the ROM a 6x or 8x
clock from which to operate. However, when the 9x over-
sampling clock (10.368 MHz) is chosen, the divide by 2 cir-
cuit is not enabled. The Tx Data is synchronized with the
Sys Clk in the following manner: When Tx PD is taken LOW,
the first edge (rising or falling) of Tx Data initializes an inter-
nal counter, so that the data bits are sampled near their
center. The power up state of the three bit memory in the
ROM filter depends on the state of Tx Data during power
down. If Tx Data is LOW when the Tx PD pin is HIGH, the
ROM filter register will be set to 010. If Tx Data is HIGH
when the Tx PD pin is HIGH, the ROM filter register will be
set to 101. This allows the filter to be set for either base
station or handset operation.
THE COMPARATOR AND ANALOG DC COMPENSATION
CIRCUIT
The high speed comparator’s threshold can be set either by
an external voltage or by using the internal DC compensa-
tion circuit. When using the internal DC compensation loop,
the received, demodulated signal is input both to the com-
parator ‘‘
a
’’ input and to the sample-and-hold (S&H) buffer
amplifier. The S&H buffer allows a single RC filter to aver-
age the DC value of the received signal without distorting it.
This DC value is connected to the ‘‘
b
’’ input of the compar-
ator. When the signal S-Field is used (named after the syn-
chronization field in DECT), this circuit can acquire the DC
voltage during the preamble and then hold it (with the exter-
nal capacitor) for the duration of the burst. This solution
avoids the problem of long strings of 1’s and 0’s that con-
ventional continuous averaging circuits have while still re-
acting quickly to acquire the proper DC average at the be-
ginning of a burst.
6
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