參數(shù)資料
型號: LMX2411
廠商: National Semiconductor Corporation
元件分類: 基帶處理器
英文描述: Baseband Processor for Radio Communications
中文描述: 基帶處理器的無線電通信
文件頁數(shù): 2/10頁
文件大?。?/td> 162K
代理商: LMX2411
LMX2411 Connection Diagram
Small Outline PackageD(SOP)
TL/W/11911–2
Top View
Order Number LMX2411M
See NS Package Number M16A
Pin Description
Pin No.
Pin Name
I/O
Description
1
Comp In
I
Positive input to the threshold comparator
2
Thresh
I/O
Negative input to the threshold comparator. This pin should be connected to a DC voltage only
if the internal DC compensation circuit is not used. When the DC compensation loop is used,
this pin should have a capacitor to ground on it.
3
V
DD
Supply voltage
4
GND
Ground
5
GND
Ground
6
DAC Out
O
Output of the Gaussian filter for modulating a VCO
7
GND
Ground
8
V
DD
Supply voltage
9
Tx PD
I
Transmitter power down. DAC is set to 128 (HEX 80) (Mid-range) when this is HIGH.
10
Sys Clk
I
Oversampling input clock from the system (9x, 12x, or 16x the bit rate). If 12x or 16x is used, the
effective sampling rate for the ROM filter is 6x or 8x, respectively.
11
Tx Data
I
Transmit data input
12
S-Field
I
DC compensation circuit enable. While LOW, the DC compensation circuit is enabled, and the
threshold is updated through the DC compensation loop. While HIGH, the switch is opened, and
the comparator threshold is held by the external capacitor.
13
Rx PD
I
Receiver power down pin; should be grounded if power down is not used.
14
Comp Out
O
Comparator output
15
ROM Sel2
I
ROM selection pin 2. Selects the oversampling clock to be used for the ROM filter.
16
ROM Sel1
I
ROM selection pin 1. Selects the oversampling clock to be used for the ROM filter.
Gaussian ROM Selection Table
ROM Sel2
ROM Sel1
Function
0
0
1
1
0
1
0
1
10.368 MHz System Clk ROM is selected
13.824 MHz System Clk ROM is selected
18.432 MHz System Clk ROM is selected
Reserved
2
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