參數(shù)資料
型號(hào)： LMX2377UTMX
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類(lèi)： XO, clock
英文描述： PLLatinum⑩ Ultra Low Power Dual Frequency Synthesizer for RF Personal Communications
中文描述： PLL FREQUENCY SYNTHESIZER, 2500 MHz, PDSO20
封裝： PLASTIC, TSSOP-20
文件頁(yè)數(shù)： 40/44頁(yè)
文件大?。?/td> 3181K
代理商： LMX2377UTMX
2.0 Programming Description
(Continued)
2.7 MAIN N REGISTER
The Main N register contains the Main N_CNTRA, Main N_CNTRB, PRE Main, and PWDN Main control words. The Main
N_CNTRAand Main N_CNTRB control words are used to setup the programmable feedback divider. The detailed description and
programming information for each control word is discussed in the following sections.
Reg. Most Significant Bit
21
20
SHIFT REGISTER BIT LOCATION
13
12
11
10
Least Significant Bit
3
2
19
18
17
16
15
14
9
8
7
6
5
4
1
0
Data Field
Address
Field
Main
N
PWDN
Main
PRE
Main
Main N_CNTRB[12:0]
Main N_CNTRA[4:0]
1
1
2.7.1 Main N_CNTRA[4:0]
The Main N_CNTRAcontrol word is used to setup the Main synthesizer’sAcounter. TheAcounter is a 5-bit swallow counter used
in the programmable feedback divider. The Main N_CNTRA control word can be programmed to values ranging from 0 to 31.
MAIN SYNTHESIZER SWALLOW COUNTER (A COUNTER)
Main N[2:6]
Divide Ratio
Main N_CNTRA[4:0]
2
0
0
1
4
0
0
1
3
0
0
1
1
0
0
1
0
0
1
1
0
1
31
2.7.2 Main N_CNTRB[12:0]
Main N[7:19]
The Main N_CNTRB control word is used to setup the Main synthesizer’s B counter. The B counter is a 13-bit programmable
binary counter used in the programmable feedback divider. The Main N_CNTRB control word can be programmed to values
ranging from 3 to 8191.
MAIN SYNTHESIZER PROGRAMMABLE BINARY COUNTER (B COUNTER)
Divide
Ratio
Main N_CNTRB[12:0]
7
6
0
0
0
0
1
1
12
0
0
1
11
0
0
1
10
0
0
1
9
0
0
1
8
0
0
1
5
0
0
1
4
0
0
1
3
0
0
1
2
0
1
1
1
1
0
1
0
1
0
1
3
4
8191
2.7.3 PRE Main
The Main synthesizer utilizes a selectable dual modulus prescaler.
MAIN SYNTHESIZER PRESCALER SELECT
Main N[20]
Control Bit
Register Location
Description
Function
0
1
PRE Main
Main N[20]
Main Prescaler
Select
16/17 Prescaler
Selected
32/33 Prescaler
Selected
2.7.4 PWDN Main
The PWDN Main bit is used to switch the Main PLL between a powered up and powered down mode.
Furthermore, the PWDN Main bit operates in conjuction with the TRI-STATE ID
o
Main bit to set a synchronous or an
asynchronous powerdown mode.
MAIN SYNTHESIZER POWERDOWN
Main N[21]
Control Bit
Register Location
Description
Function
0
1
PWDN Main
Main N[21]
Main Powerdown
Main PLL Active
Main PLL
Powerdown
L
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相關(guān)PDF資料
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